Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by N 2 -tra...

Neuromorphic networks of high connectivity may be implemented using CMOS circuits as cell bodies, nanowires as axons and dendrites, and self-assembled single-molecule latching switches as synapses. The integration scale of such “CrossNet” circuits of acceptable size (~30×30 cm2) may be comparable with that of the mammal’s cerebral cortex (up to 1010 neurons), despite the quasi-2D structure of t...

We have calculated the minimum chip area overhead, and hence the bit density reduction, that may be achieved by memory array reconfiguration (bad bit exclusion), combined with error correction code techniques, in prospective terabit-scale hybrid semiconductor/nanodevice memories, as a function of the nanodevice fabrication yield and the micro-to-nano pitch ratio. The results show that by using ...

Architectures built using bottom-up self-assembly of nanoelectronic devices will need to tolerate defect rates that are orders of magnitude higher than those found in current CMOS technologies. In this paper, we describe and evaluate an approach to provide defect isolation in such an architecture that consists of a large number of simple computational nodes, each of which can communicate with f...

This paper provides detailed simulation results and analysis of the prospective performance of hybrid CMOS/nanoelectronic processor systems based upon the field-programmable nanowire interconnect (FPNI) architecture. To evaluate this architecture, a complete design was developed for an FPNI implementation using 90 nm CMOS with 15 nm wide nanowire interconnects. Detailed simulations of this desi...

In recent years, size of VLSI circuits is dramatically grown and layout generation of current circuits has become a dominant task in design flow. Standard cell placement is an effective stage of physical design and quality of placement affects directly on the performance, power consumption and signal immunity of design. Placement can be performed analytically or heuristically. Analytical placer...

The frequency-dependent characteristics of microstrip planar circuits have been previously analyzed using several full-wave approaches. All those methods directly give characteristic of the circuits frequency by frequency. Computation time becomes important if these planar circuits have to be studied over a very large bandwidth. The transmission line matrix (TLM) method presented in this paper ...

Resonant tunneling diodes (RTDs) have intriguing properties which make them a primary nanoelectronic device for both analog and digital applications. We propose a bistable RTD-based cell for the cellular neural network (CNN) which exhibits superior performance in terms of circuit complexity, and processing speed compared to standard cells.

Radial core/shell nanowires (NWs) represent an important class of one-dimensional (1D) systems with substantial potential for exploring fundamental materials electronic and photonic properties. Here, we report the rational design and synthesis of InAs/InP core/shell NW heterostructures with quantum-confined, high-mobility electron carriers. Transmission electron microscopy studies revealed sing...

microscopy-based techniques is enabling new ways to build and investigate nanoscale electronic devices. Here we review several advanced techniques to characterize and manipulate nanoelectronic devices using an atomic force microscope (AFM). Starting from a carbon nanotube (CNT) network device that is fabricated by conventional photolithography (micron-scale resolution) individual carbon nanotub...