In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches the technology, high turn-on/off capacitance ratio of LC-tank switched capacitors, addition to adjustable magnetic coupling technique, yields alm...