In the today’s era, reversible logics are the promising technology for the designing of low power digital logic system having major application in the field of nanotechnology, quantum computation, DNA and other low power digital circuits. Reversible logics provide zero power dissipation (Ideally) in the digital operations. There are numbers of circuit designed by the reversible logics and seque...

This paper presents low power operation of barrel shifter and rotator which are designed and simulated in 2 phase clocked adiabatic static CMOS logic. The power consumption of the circuits is compared with that of static CMOS logic. A barrel logic right shifter, a right rotator and shift/rotator are simulated in 45nm CMOS process technology. A mux based design is used for all the above circuits...

This paper describes the development of notch filters and dichroic beam-splitters, the latter to be a visible 2-channel WDM Multiplexer/Demultiplexer (MUX/DEMUX). Both discrete devices are intended to be used on very short-haul links based on Poly-Methyl-Methacrylate (PMMA) Polymer Optical Fibres (POFs). The filters were built from commercially available multilayer dielectric stack and also fro...

We present dual-polarization QPSK link transmission performance below the FEC limit with simultaneous transmission of three OAM states carrying 14×10-GBd WDM channels using silica 2D-3D hybrid integrated devices for OAM state multiplexing/demultiplexing capacity of 1.68 Tb/s. OCIS codes: (060.1660) Coherent communications; (050.4865) Optical vortices; (060.4230) Multiplexing Currently, space-di...

Two silicon, 4? O-band multiplexers (MUXs) for 400GbE using two Mach-Zehnder interferometers (MZIs) having 90-degree phase shift in their output with the help of on-chip polarization multiplexing are demonstrated. By 2 × and 1 MZIs first 3200-GHz filters, relative position spectra has difference, leading to significant simplification tuning peak wavelength filters. The MUX is done by an polariz...

The DS40MB200 is a dual 2:1 multiplexer and 1:2 fan-out repeater designed to support redundancy and extending copper backplane to data rates up to 4 Gb/s. With input equalization and output pre-emphasis, the DS40MB200 is capable of compensating attenuation distortion and reducing deterministic jitter caused by bandwidth-limited transmission lines. This application note outlines the methods to s...

After structural synthesis, an appropriate gate-level structure has to be found. While the controller can be synthesized quickly the datapath might become too large so that a partitioning step has to be carried out. As pointed out above, our approach tries to minimize the number of tasks for logic synthesis (i.e. the number of blocks) while achieving a close to optimum realization. This is done...

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design mandatory for efficient systems. In designing low-energy dissipation circuits, reversible logic more than irreversible circuits but at cost higher complexity. This paper introduces an signed/unsigned 4 × Vedic multiplier with minimum quantum cost. The considered fast a...

We designed and experimentally demonstrated an ultra-compact ultra-broadband two-mode de-multiplexer based on a subwavelength grating (SWG) asymmetrical coupler (ADC) silicon-on-insulator (SOI) platform. The device consists of cascaded strip waveguide tapered to multimode segment SWG-based single-mode waveguide. Tapering the in multi-segments guarantees high fabrication tolerance with wider wav...

In this paper, an analytical delay model of Source-Coupled Logic (SCL) gates is proposed. In particular, the multiplexer, the XOR and the D-latch gates are considered. The method starts from a linearization of SCL gates, and analysis of the equivalent circuit obtained is simplified by introducing the dominant-pole approximation. The delay expression obtained is quite simple and each term has an...