Performance evaluation, using both analytical and simulation models, of multistage priority interconnection networks with a single layer or more layers is presented. The configurations of the networks under study apply a conflict drop resolution strategy. Our analytical models are based on a more realistic assumption. A new analysis is given and is verified by simulation results. In single netw...

1383-7621/$ see front matter 2010 Elsevier B.V. A doi:10.1016/j.sysarc.2010.05.006 * Corresponding author. Tel.: +34 868884638; fax: E-mail addresses: [email protected] (A. Flo (M.E. Acacio), [email protected] (J.L. Aragón). High performance processor designs have evolved toward architectures that integrate multiple processing cores on the same chip. As the number of cores inside a Chip Mu...

We have been investigating alternatives to conventional benchmarking that will allow users and machine designers to characterize the performance space of the memory hierarchy and the interconnection network of different shared memory machines in a uniform way, while providing a level of detail that is usually associated with hardware monitors. Our approach uses micro benchmarks (small benchmark...

Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some ...

This paper proposes a new protocol for maintaining cache coherence in a large multiprocessor system. The study focuses on systems with private caching that use a multistage network to interconnect the processors. The protocol, called the Distributed Directory Scheme, distributes part of the directory information into the interconnection network switches. The redistribution of the directory info...

Oh, D.H., J.H. Nang, H. Yoon and S.R. Maeng, An efficient mapping of Boltzmann Machine computations onto distributedmemory multiprocessors, Microprocessing and Microprogramming 33 (1991/92) 223-236. In this paper, an efficient mapping scheme of Boltzmann Machine computations onto a distributed-memory multiprocessor, which exploits the synchronous spatial parallelism, is presented. In this schem...

Cube based networks have received much attention over the past decade since they offer a rich interconnected structure with a number of desirable properties such as low diameter, high bisection width, lesser complexity and Cost. Among them the hypercube architecture is widely used network for parallel computer system due to its low diameter. The major drawback of hypercube based architectures i...

In this paper we present a general framework for architectural design of large hierarchical multiprocessor systems under rapidly changing packaging, processor, and in-terconnection technologies. Processor boards with larger area (A) and greater pinouts are becoming feasible. Board interconnection technology has advanced from only peripheral connections O(p A) to elastomeric surface connections ...

This paper describes a generalized sequential diagnosis algorithm whose analysis leads to strong diagnosability results for a variety of multiprocessor interconnection topologies. The overall complexity of this algorithm in terms of total testing and syndrome decoding time is linear in the number of edges in the interconnection graph and the total number of iterations of diagnosis and repair ne...

Simple Serial Synchronized (SSS) Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called the SNAIL with the SSS-MIN are p...