نتایج جستجو برای: multiplier

تعداد نتایج: 10068  

2016
C Vivek R. Subalakshmi

JCHPS Special Issue 8: December 2016 www.jchps.com Page 9 Design of Low-Power Specific Parallel Array Multipliers C Vivek*, R. Subalakshmi Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Tamil Nadu. *Corresponding author: E-Mail: [email protected] ABSTRACT Multipliers play a critical part in recent digitalized life. In this advanced spher...

1999
Vesselin K. Vassilev Julian Francis Miller Terence C. Fogarty

The two-bit multiplier is a simple electronic circuit, small enough to be evolvable, and practically useful for the implementation of many digital systems. In this paper, we study the structure of the two-bit multiplier fitness landscapes generated by circuit evolution on an idealised model of a field-programmable gate array. The two-bit multiplier landscapes are challenging. The difficulty in ...

2011
B.Ramkumar V.Sreedeep Harish M Kittur

AbstractIn this work faster column compression multiplication has been achieved by using a combination of two design techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using a hybrid adder proposed in this work. Based on the proposed techniques 8, 16, 32 and 64bit Dadda multipliers are developed and com...

2013
Nirmal kumar Dhivya Dr. G. M. Tamilselvan

For high speed applications, a huge number of adders or compressors are to be used in multiplications to perform the partial product addition. In this paper a new approach of reducing power for a given system is developed that is adiabatic logic. The Array multiplier, Vedic 4x4 multiplier and 8x8 multiplier are designed using energy recovery logic in the inverter. The number of adders is reduce...

2014
Shubhi Shrivastava Pankaj Gulhane

This paper describes optimized radix-4 booth multiplier algorithm for multiplication of two binary numbers on VHDL device. Radix-4 Booth’s algorithm is presented as an alternate solution of basic binary multiplication, which can help in reducing the number of partial products by a factor of 2. Radix-4 Booth’s multiplier alters the way of addition of partial products thereby using Carry-Save-Add...

Journal: :bulletin of the iranian mathematical society 2011
b. mashayekhy f. mohammadzadeh

2015

Multiplication is frequently required in digital signal processing. Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. In most signal processing applications, a rounded product is desired to avoid growth in word size. Thus an important design goal is to reduce the area requirement of the rounded output multiplier. This paper pre...

2015
Sunil Devidas Bobade Vijay R. Mankar

Elliptic Curve Cryptography is one of the most preferred public key Cryptography algorithms known for its security strength and reduced key size. This makes ECC most suitable for implementing the hardware security chip for providing security services in portable embedded devices. This paper presents an area efficient Security Chip housing ECC algorithm for data encryption over binary field and ...

2011
Asmita Haveliya

In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per The proposed architecture, for two 8-bit numbers; th...

2013
Teffi Francis Jobin K. Antony

Braun multiplier is one of the parallel array multipliers, which is used for unsigned numbers multiplication. This paper presents different techniques for optimizing the multiplier in power and delay parameters. The dynamic power of a multiplier can be reduced by using bypassing techniques and delay can be reduced by replacing ripple carry adder in the last stage of full adders by optimized add...

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