Typically real-time applications are written in a multi-threaded language and are executed on single threaded control-ow (von Neumann) processors. A software scheduler is used to switch between the application's multiple threads, thereby simulating a multi-threaded processor. Unfortunately software scheduling is problematic if real-time constraints are to be guaranteed and therefore static (pre...

The architecture of a new associative processor array chip, GLiTCH, is outlined. The suitability of such arrays for image processing and computer vision work is stressed, and a general purpose vision processing module, currently being designed, is described. Effective programming of bit-serial procssor arrays requires an efficient library of low-level routines, especially for operations such as...

This paper1 focuses on the problem of providing isolation and real-time execution in scheduling multi-thread applications on a single processor. The proposed scheduling algorithm can be applied in a wide range of different situations, such as in a multimedia real-time systems, where applications may require a guaranteed level of Quality of Service, or in a network link, where different flows of...

The task parallelization is proposed in the OpenMP3.0 specification, which aims to resolve the irregular parallel computing problems. This paper presents the novel irregular application task model on Cell BE processors, which could reduce the difficulty of irregular applied parallel programming. In this Model, the two kinds of optimization techniques for maximum task numbers and maximum recursi...

The paper presents the results of investigations concerning the possibility of using programmable logic devices (FPGA) to build virtual multi-core processors dedicated specifically towards particular applications. The paper shows the designed architecture of a multi-core processor specialized to perform a particular task, and it discusses its computational efficiency depending on the number of ...

The report describes an environment for performing experiments in distributed processing. It replaces an earlier (1985) report, reflecting changes in the system and terminology. Our system offers researchers an easy way to design, implement, and test parallel algorithms. It provides software tools which make possible a variety of connection structures between processes. These process structures...

The design, implementation, and performance of two chess programs running on a multi-processor system are presented. Methods for distributing and enhancing the alpha-beta algorithm in a parallel environment are discussed. With the Principal Variation Splitting method, a four processor chess program yields a 3.35 fold speed-up over the sequential version. [Recreated from files dated 4 May 1984 i...

This paper describes a processor architecture designed specifically to perform input/output and interfacing functions for any central-processor-peripheral configuration. This architecture is justified on the basis of functional I/O requirements which are discussed in detail. This processor is microprogrammable with a writeable control store, allowing dynamic configuration of the processor for d...

This paper provides an overview of the Naval Postgraduate School ARIES autonomous underwater vehicle. An attempt is made to highlight its’ current operational capabilities and provide a description of future enhancements for greater mission utility and flexibility. An overview of the vehicle design along with descriptions of all major hardware components and sensors is given. A major discussion...

In this paper we propose a blocking-aware partitioning algorithm which allocates a task set on a multiprocessor (multi-core) platform in a way that the overall amount of blocking times of tasks are decreased. The algorithm reduces the total utilization which, in turn, has the potential to decrease the total number of required processors (cores). In this paper we evaluate our algorithm and compa...