Repairable standby system’s study and analysis is an important topic in reliability. Analytical techniques become very complicated and unrealistic especially for modern complex systems. There have been attempts in the literature to evolve more realistic techniques using simulation approach for reliability analysis of systems. This paper proposes a hybrid approach called as Markov system ...

One of the major reliability concerns in nano-scale VLSI design is the time dependent Negative Bias Temperature Instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, f...

In this project, we present an adaptive body biasing scheme for standby leakage reduction in the cache memories. During standby, the memory cells are in reverse body bias mode while during active mode a selected portion of the memory cells are driven to zero body bias. The main advantage of this scheme is zero delay penalty when compared to conventional design because of the fact that the cells...

In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression drive...

This paper presents an ultra-low-standby-power radio transmitter that was designed for applications with extreme energy storage and/or energy harvesting constraints. By utilizing aggressive power gating techniques within a low-complexity architecture featuring only a single RF stage, the transmitter achieved a standby power consumption of 39.7 pW. The architecture employed a direct-RF power osc...

For low power circuits downscaling of MOSFET has a major issue of scaling of voltage which has ceased after 1V. This paper highlights comparative study and analysis of pocket double gate tunnel FET (DGTFET) with MOSFET for low standby power logic circuits. The leakage current of pocket DGTFET and MOSFET have been studied and the analysis results shows that the pocket DGTFET gives the lower leak...

This paper proposes a comprehensive SRAM cell optimization scheme that minimizes leakage power under ultra-low standby supply voltage (VDD). The theoretical limit of data retention voltage (DRV), the minimum VDD that preserves the states of a memory cell, was derived to be 50 mV for an industrial 90 nm technology. A DRV design model was developed on parameters including body bias, sizing, and c...