This paper describes a comparator that uses a gain stage as a preamplifier in the preamplification mode and as a latch in the latch mode. This method effectively reduces the power consumption of the comparator. Using a 1.2um CMOS process and applying offset cancellation to all of the circuit, an offset of less than 100uV at comparison rates up to 6MHz, with only a 130uW power dissipation and 3V...

Dynamic comparators are used in high speed analog to digital converters. In this paper low voltage, low power dynamic comparators are designed in 130 nm technology and the analysis of the power consumption and delay will be presented. Based on the presented analysis, a new dynamic comparator is proposed. By using power gating technique and adding few transistors, the positive feedback during th...

This Paper introduced a 4 bit Flash Analog to Digital converter. The propose ADC consist of the comparators and the MUX based decoder. Propose Comparator eliminate the use of resistor ladder in the circuit. All the input of comparators are connected to the common input node. Depending upon the internal voltage of comparator and the input voltage output may be “0” or “1” known as thermometer cod...

We present a methodology to reduce the charge injection noise for an offset-free comparator, so as to achieve a higher resolution. Our method incorporates an algorithm that automatically searches for the optimal transistor sizes of a switch in the comparator. The values of this methodology are in two aspects. First of all, it takes away from designers the burden of sizing the transistors. Secon...

In present era, development of digital circuits, signal processors and other integrated circuits, magnitude comparators are challenged by large area and more power consumption. Comparator is most basic circuit that performs comparison. This paper presents a technique to design a two bit comparator which consumes less area and power. DSCH and MICROWIND version 3 are used to design the schematic ...

A b s t r a c tAn idea of using 1:1 comparison for 10:1 and 1:10 impedance transfer is described in the paper. Results of measurements performed for 10:1 transfer of inductance are discussed. The results achieved prove that using 1:1 comparator bridge and applying proposed procedure is possible to transfer unit to the objects of 10 times smaller values with relative uncertainty only a little hi...

With only a few exceptions the minimum-comparator N-sorter networks employ the generalized "divide-sort-merge" strategy. That is, the N inputs are divided among g 2 2 smaller sorting networks -of size N1’N2’...‘Ng9 where N = g ck~1 Nk -that comprise the initial portion of the N-sorter network. The remainder of the N-sorter is a comparator network that merges the outputs of the Nl-, N2-, . . . ....

In Analog to digital convertor design converter, high speed comparator influences the overall performance of Flash/Pipeline Analog to Digital Converter (ADC) directly. This paper presents the schematic design of a CMOS comparator with high speed, low noise and low power dissipation. A schematic design of this comparator is given with 0.18μm TSMC Technology and simulated in cadence environment. ...

In this paper we give a systematic method to design Self Exercising (SE) [ 11 self testing k-order comparators. The k-order comparator is defined as a combinational circuit that compares two operands and decides if these differ in less than k bits. According to this definition the usual equality comparator is the 1st-order comparator. Also in this paper we discuss the applicability of the k-ord...

This article presents a novel approach for readability assessment through sorting. A comparator that judges the relative readability between two texts is generated through machine learning, and a given set of texts is sorted by this comparator. Our proposal is advantageous because it solves the problem of a lack of training data, because the construction of the comparator only requires training...