this paper proposes a flexible power electronic transformer (fpet) for the application in the micro-grids. the low frequency transformer is usually used at the point of common coupling (pcc) to connect the low voltage grid and utility network to each other. the conventional 50hz transformer results in enhanced low voltage-grid power management system during grid-connected operation. in this pap...

The proposed scheme, called the IOC-LP (input reduction and one block compression for low power test), compresses the test data of scan based SoCs to improve the compression ratio in the ATPG process. It does so by using the modified input reduction and novel techniques, a new scan flip-flop reordering for low power test, the newly proposed one block compression, and a novel reordering algorith...

0740-7475/01/$10.00 © 2001 IEEE November–December 2001 THE 2001 International Technology Roadmap for Semiconductors (ITRS) identifies key manufacturing issues and highlights the cost of test and the associated cost of test equipment. As our analysis of prior roadmap data in Figure 1 (next page) shows, the cost of testing a transistor will equal the cost of fabricating it by around 2012. Traditi...

Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and improving the yield. Our research addresses this problem by proposing a new method which maintains the benefits of mixed-mode built-in self-test (BIST) (low test application time and high fault coverage), and reduces the...

Test power and test time have been the major issues for current scenario of VLSI testing. The test data compression is the well known method used to reduce the test time. The don’t care bit filling method can be used for effective test data compression as well as reduction in scan power. In this paper we describe the algorithm for don’t care assignment like MT(Minimum Transition)-fill technique...

Abstact A new design approach is proposed for a fault coverage circuit. In this design a linear feedback shift register which is called as LT_LFSR (Low Transition Linear Feedback Shift Register) is used. Using LT_LFSR reduces the power consumption by reducing the number of transitions during test mode. Power reduction is done by implementing two new test pattern generation methods in LFSR. In b...

Information on statistical power is critical when planning investigations and evaluating empirical data, but actual power estimates are rarely presented in population genetic studies. We used computer simulations to assess and evaluate power when testing for genetic differentiation at multiple loci through combining test statistics or P values obtained by four different statistical approaches, ...