We propose a mathematical framework to deal with the composition of heterogeneous reactive systems. Our theory allows to establish theorems, from which design techniques can be derived. We illustrate this by two cases: the deployment of synchronous designs over GALS architectures, and the deployment of synchronous designs over the so-called Loosely Time-Triggered Architectures.

Every user of programmable logic at some point faces the question: “How large a device will I require to fit my design?” In an effort to provide guidance to their users, Field Programmable Gate Array (FPGA) manufacturers, including Xilinx, describe the capacity of FPGA devices in terms of “gate counts.” “Gate counting” involves measuring logic capacity in terms of the number of 2-input NAND gat...

Two regular circuit structures based on the programmable logic array (PLA) are proposed. They provide alternatives to the widely used standard-cell structure and have better predictability and simpler design methodologies. A whirlpool PLA is a cyclic four-level structure, which has a compact layout. Doppio-ESPRESSO, a four-level logic minimization algorithm, is developed for the synthesis of Wh...

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were conne...

Recent progress in DNA micro-array techniques enables us to obtain a massive amount of gene expression profiles simultaneously. Using the expression profiles we infer a gene network hiding the obtained data. Although several inference methods have been presented, most of them are insufficient in terms of reliability and processing time [1]. To overcome the problem, we develop an inference engin...

FPGA is a 2D array of configurable logic blocks. Packing is to pack logic elements into device specific configurable logic blocks for subsequent placement. The traditional fixed delay model of inter and intra cluster delays used in packing does not represent post-placement delays and often leads to sub-optimal solutions. This paper presents a new layout driven packing algorithm, named LDPack, b...

We describe the control and performance of a new near-infrared camera based on a Rockwell PICNIC array detector for interferometry observations at the Infrared-Optical Telescope Array (IOTA). The camera control uses a complex programmable logic device that allows fast and stable clocking of the PICNIC array and on-the-fly reconfiguration of the readout method. We measured a read noise as low as...

We present an application specific, asynchronous VLSI processor array for the dynamic programming algorithm for the 0/1 knapsack problem. The array is derived systematically, using correctnesspreserving transformations, in two steps: the standard (dense) algorithm is first transformed into an irregular (sparse) functional program which has better efficiency. This program is then implemented as ...

In this paper circuit implementations of cellular processor arrays intended for image processing applications are discussed. It is demonstrated that a departure form the standard CNN model can lead to a significant improvement when processing binary (black/white) images. An asynchronous cellular logic array circuit is presented, which is capable of simulating trigger-waves in an excitable mediu...

We have developed an active matrix-addressed magneto-optical spatial light modulator driven by spin-transfer switching (spin-SLM) which has a 100 × 100 array pixel layout with a 2 μm pixel pitch. It has pixel-selection-transistors and logic circuits which convert serial data into parallel data to reduce input terminals. We have confirmed successful magnetization switching of each pixel by injec...