Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is b...

This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz ...

This paper investigates the performance of the Kalman filter as a timing recovery system in tracking mode, subject to a wide range of operating conditions. Our simulation compares the Kalman filter and the phase-locked loop based on the number of divergences for various values of timing disturbance and SNR. They are shown to work equally well in low SNR and disturbance. However, the Kalman filt...

In this work, a Markov random field based phase locked loop is proposed for phase unwrapping. The neighboring pixels are used to update the phase estimate of the centering pixel. The performance of the proposed method is evaluated for both synthetic and real interferometric phase. For terrains with relatively low slopes, the phase unwrapping is done successfully. However, in case of high fringe...

The precision of phase-locked loop (PLL) has a direct effect on the output performance for three-phase grid-connected inverter or three-phase active PFC. In this paper, a new three-phase digital closed-loop phase-locked algorithm is proposed on the basis of synchronous reference frame transformation. Synchronous simulation of the PLL techniques is a good choice even if the polluted three-phase ...

An ASIC design of Dual Edge Triggered Phase Detector(DET PD) for Delay locked loop(DLL) and Phase locked loop(PLL) applications is proposed in this paper.The proposed DET PD has high locking speed and less jitter. The designs are based on TSPC flip flop logic, which overcomes the issue of narrow capture range. The Double edge triggered phase detector dissipates less power than conventional desi...

In this paper we describe a new architecture of a frequcncy-lo-voltage convcrtcr VVC) :md iLs high frequency intcgrated applications. The circuit is of a rcduccd complexity and its CMOS implcmcnlalion requires a very small area. Besides its small integration arca, thc circuit is vcry fast and has many inlcrcsting high frequcncy applications. This FVC is used to build an integrated high-precisio...

This work aims at analyzing three different techniques for synchronizing RF oscillators. These techniques are Injection Locking (ILO), Phase Locked Loop (PLL) and Injection Locked Phase Locked Loop (ILPLL). ILPLL, which is a combination of PLL and ILO, has superior noise performance –compared to all the restat medium frequency offsets and the same noise performance at low and high offsets. Furt...

The laser line-width required in PSK homodyne communication systems with Dither phase-locked loop receivers are exactly evaluated. It is shown that second-order phase-locked loops require at least 0.2 pW of signal power per every Hz of laser line-width (this number refers to the system with the detector responsivity 0.94 A/W, damping ratio 0.707, and the phase error standard deviation 10°). Thi...

A method for shortening of the settling time in all digital phase-locked loops is proposed. The method utilizes self monitoring to obtain the parameters necessary for feed-forward compensation. Analysis shows that by employing this technique both fast settling and good stability can be achieved simultaneously. Matlab and Verilog-AMS simulation shows that typical settling speed can be reduced to...