In order to meet the requirements for future satellite applications, a brassboard of an extremely reliable fault-tolerant spaceborne computer (FTSC) has been developed by Raytheon Co., Sudbury, MA., under the sponsorship of the USAF/SAMSO. The requirements for the FTSC were high reliability, high speed, low power, high density and tolerance to space radiation environments. The reliability requi...

Integrated circuits are often designed using simple and conservative 'design rules' to ensure that the resulting circuits will meet reliability goals. This simplicity and conservatism leads to reduced performance for a given circuit and metallization technology. To address this problem, we had developed a TCAD tool, ERNI, which allows process-sensitive and layout-specific reliability estimates ...

The analog IC technology, might sound old-fashioned, is still important for the future wireless systems such as 4G cellular phone systems, broadband wireless networkings, and wireless sensor networkings. The analog features and issues of the scaled CMOS transistor, the basic issue and the technology trend for the ADC as an important building block of wires systems, and the feature of the digita...

Dimensional scaling of interconnects at future technology generations presents major limitations to the improvement of the performances of integrated circuits. In this paper, we investigate the impact of highly scaled Cu/low-κ interconnects on the speed and power dissipation of multiple circuit blocks based on timing-closed full-chip Graphic Database System II (GDSII)-level layouts with detaile...

This paper presents the design and fabrication of a feed horn antenna integrated fix-tuned 380GHz sub-harmonically pumped mixer, based on planar GaAs air-bridged Schottky anti-parallel diode from Rutherford Appleton Laboratory. The diode was designed and fabricated by millimeter technology group, Rutherford Appleton Laboratory, UK. The mixer’s circuit configuration and cavity block are realized...

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects i...

Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. It is highly desirable to automate the transistor sizing process towards being able to rapidly design high performance integrated circuit. Presented here is a simple but effective algorithm for automatically optimizing the circuit parameters by exploiting the ...