System designers conceptualize designs at an abstract functional level where outputs are typically described as (algorithmic or transfer) functions of the system inputs. This design abstraction level, called electronic system level (ESL), enables ease of design capture and early design space exploration of multiple design implementation alternatives. ESL designs can be refined into lower levels...

We show a generic describing method of hardware including a memory access controller in a C-based high-level synthesis technology (Handel-C). In this method, a prefetching mechanism to improve the performance by hiding memory access latency can be systematically described in C language. We demonstrate that the proposed method is very simple and easy through a case study. The experimental result...

A conventional binding method for low power in a high-level synthesis mainly focuses on finding an optimal binding for an assumed input data, and obtains only one binding table. In this paper, we show that a binding method which uses multiple binding tables gets better solution compared with the conventional methods which use a single binding table, and propose a dynamic bus binding scheme for ...

We investigate a two-level hierarchical architecture for hybrid control. On the top level, a discrete supervisory controller acts on quantised measurement information by switching between a finite number of continuous controllers in order to enforce a language inclusion specification. A widely accepted approach to this problem is to first construct a discrete abstraction of the continuous low-l...

We present a hardware synthesis system that accepts system-level speciications in both Verilog HDL and C. A synchronous semantics is assumed for both languages in order to guarantee a uniform underlying model. The rationale for mixed input speciications is to support hardware/software co-design by allowing the migration to hardware of system modules originally described in the C language. We di...

This paper describes a new and eeective approach to register and interconnect optimisation, which is applicable in a dual context : to reduce chip area in high-level synthesis, and to reduce resource load (and thus execution time) in retargetable code generation. The key idea is to carefully optimise the way in which data is transferred between functional units. The impact on high-level synthes...

A new probabilistic algorithm, called Probabilistic Rejectionless Anti-Voter (PRAV), is introduced. Due to its property to concentrate computational efforts on places where there are the greatest chances for the improvement of an objective function and due to the employed rejectionless mechanism a significant speed-up over other probabilistic methods is achieved The extensive superior experimen...

Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iteration, and significant improved fault coverage. In this paper, we present a novel register allocation method, which is based on weighted graph coloring algorithm, targeting testability improvement for digital circuits....

The recent progress of high level synthesis has illuminated an effective aid for system designers. To keep pace with the development of such an environment, there is a need to consider design for testability (DFT) during the synthesis process. This paper proposes a DFT scheme that can be coordinated with data path synthesis by an interactive trade-off process. The basis of this work is a system...