This paper is investigated the low frequency noise behavior in subthreshold regime of gate-all-around silicon nanowire field effect transistors. Downscaling of multi gate structure beyond 50 nm gate length describes the quantum confinement related model. A drain current model has been described for output characteristics of silicon nanowire FET that is incorporated with velocity saturation effe...

This work demonstrates two DNA-based logic circuits that behave as a half-adder and a half-subtractor. A half-adder is composed of an AND gate and an XOR gate, whereas a half-subtractor consists of an INH gate and an XOR gate. The proposed designs are inspired by molecular beacons.

In this paper, we propose a novel design analysis for a Junctionless Double Gate Vertical MOSFET (JLVMOS) with metal gate electrode and HfO2, for which the simulations have been performed using TCAD (ATLAS), The simulated results exhibits significant improvements in comparison to conventional JLVMOS device with a polysilicon gate electrode and ITRS values for different node technology . In plac...

Abstract— In this paper, the researchers propose the design of reversible circuits using reversible gates. Reversible logic is implemented in reversible circuits. Reversible logic is mostly preferred due to less heat dissipation. Conservative logic gates can be designed in any sequential circuits and can be tested using two test vectors. The significance of proposed work lies in the design of r...

Abstract – Numerical simulations of In0.52Al0.48As/In0.7Ga0.3As/InP HEMTs have been carried out with a 2D/3D-hydrodynamic model. The investigation of double gate and striped-channel devices with the same layer structure results in an increase of cut-off frequencies. At a reduce of gate lengths down to 5 nm short channel effects becomes important in particular for the single gate device. Transis...

A set of different short term stress conditions are applied to AlGaN/GaN high electron mobility transistors and changes in the electronic behaviour of the gate stack and channel region are investigated by simultaneous gate and drain current low frequency noise measurements. Permanent degradation of gate current noise is observed during high gate reverse bias stress which is linked to defect cre...

Airport gate assignment is to appoint a gate for the arrival or leave flight and to ensure that the flight is on schedule. Assigning the airport gate with high efficiency is a key task among the airport ground busywork. As the core of airport operation, aircraft gate assignment is known as a kind of complicated combinatorial optimization problem. This paper proposed robust assignment model to m...

| The incessant traffic of ions across cell membranes is controlled by two kinds of border guards: ion channels and ion pumps. Open channels let selected ions diffuse rapidly down electrical and concentration gradients, whereas ion pumps labour tirelessly to maintain the gradients by consuming energy to slowly move ions thermodynamically uphill. Because of the diametrically opposed tasks and th...

The end of the roadmap for planar single-gate (SG) CMOS seems to be drawing nearer as the industry increases research activities in double-gate (DG) and multi-gate (MG) CMOS novel device structures. Therefore, this paper will focus on how to extend the life of planar SG CMOS through 2016 and accelerate the understanding & realization of MG CMOS by 2007 through the use of advanced ion implantati...

We have studied electron mobility behavior in asymmetric double-gate silicon on insulator ~DGSOI! inversion layers, and compared it to the mobility in symmetric double-gate silicon on insulator devices, where volume inversion has previously been shown to play a very important role, being responsible for the enhancement of the electron mobility. Poisson’s and Schroedinger’s equations have been s...