This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third unit can perform arithmetic operations such as addition, subtraction, multipl...

[Purpose] This study investigated the association between floating toe and toe grip strength. [Subjects and Methods] A total of 635 Japanese children aged 9-11 years participated in this study. Floating toe was evaluated using footprint images, while toe grip strength was measured using a toe grip dynamometer. All 1,270 feet were classified into a floating toe group and a normal toe group accor...

Due to technological advances, it has become possible to implement floating-point cores on FPGAs in an effort to provide hardware acceleration for the myriad applications that require high performance floating-point arithmetic. However, in order to achieve a high clock rate, these floating-point cores must be deeply pipelined. Due to this deep pipelining and the complexity of floating-point ari...

The latest Graphics Processing Units (GPUs) are reported to reach up to 200 billion floating point operations per second (200 Gflops 19) and to have price performance of 0.1 cents per M flop. These facts raise great interest in the plausibility of extending the GPUs’ use to non-graphics applications, in particular numerical simulations on structured grids (lattice). In this paper we (1) review ...

This paper analyzes the dynamic incentives for technology adoption under a transferable permits system, which allows for strategic trading on the permit market. Initially, firms can both invest in low– emitting production technologies and trade permits. In the model, technology adoption and allowance prices are generated endogenously and are inter–dependent. It is shown that the non–cooperative...

In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable precision floating point multiplication such as multi-media processing applications. In the proposed architecture/methodology, we propose the replacement of exis...

Cell fate decisions in early embryonic cells are controlled by interactions among developmental regulatory genes. Zebrafish floating head mutants lack a notochord; instead, muscle forms under the neural tube. As shown previously, axial mesoderm in floating head mutant gastrulae fails to maintain expression of notochord genes and instead expresses muscle genes. Zebrafish spadetail mutant gastrul...

A new generation method to implement CMOS floating resistors is presented. The generation method depends on the linearization of the differential current of two matched NMOS transistors in two alternative configurations. The CMOS floating resistors implemented are based on using MOS transistors operating in the saturation region with their sources connected to their substrates. New CMOS floatin...

New Voltage Differencing Differential Input Buffered Amplifier (VD-DIBA) based lossless grounded and floating inductance simulation circuits have been proposed. The proposed grounded simulated inductance circuit employs a single VD-DIBA, one floating resistance and one grounded capacitor. The floating simulated inductance (FI) circuits employ two VD-DIBAs with two passive components (one floati...

It is proposed to add to the C++ standard optional floating-point typedefs having specified widths. The optional typedefs include float16_t, float32_t, float64_t, float128_t, their corresponding least and fast types, and the corresponding maximumwidth type. These are to conform with the corresponding specifications of binary16, binary32, binary64, and binary128 in IEEE_ floating-point format. T...