The electrical behaviour of organic memory structures, based on single-walled carbon-nanotubes (SWCNTs), metal-insulator-semiconductor (MIS) and thin film transistor (TFT) structures, using poly(methyl methacrylate) (PMMA) as the gate dielectric, are reported. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated alumini...

Single Electron Transistor (SET) is an advanced technology for future low power VLSI devices. SET has high integration density and a low power consumption device. While building logic circuits that comprise only of SETs, it is observed that the gate voltage at the input must be higher than the power supply of SET for better switching characteristics. This limitation of SET in the power and gate...

We report the use of inelastic electron tunneling spectroscopy ~IETS! as an effective tool in studying traps in high-k gate dielectrics, particularly the electrical stress-induced traps, in metal–oxide– semiconductor ~MOS! structures. Two kinds of traps may be identified by the IETS technique: ~1! those that contribute to trap-assisted conduction mechanisms and ~2! those that contribute to trap...

Floating-gate (FG) transistors serve as attractive media for non-volatile storage of analog parameters. However, conventional FG current memories when used for storing sub-threshold currents are sensitive to variations in temperature which limit their applications to controlled environments. In this paper, we propose a temperature compensated, high-density array of FG current memories that can ...

Polysilicon depletion effects show a strong gate length dependence according to experimental p-channel MOS capacitance–voltage ( – ) data. The effect can be influenced not only by gate geometries, but also by dopant profiles in poly-gates. These effects have been modeled and verified using device simulation. Nonuniform dopant distributions in the vertical and lateral direction in the poly-gate ...

The influence of gate direct tunneling current on ultrathin gate oxide MOS ( nm nm, – nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low static-logic circuits. However, dynamic logic and analog circuits are more significantly influence...

Gate tunneling current in fully depleted, double-gate (DG) silicon-on-insultor (SOI) MOSFETs is characterized based on quantummechanical principles. The gate tunneling current for symmetrical DG SOI with ground-plane ( =1.5 nm and =5 nm) is shown to be higher relative to single-gate (bulk) MOS structure. The tunneling is enhanced as the silicon layer becomes thinner since the thinner silicon la...

Germanium (Ge) has gained great attention not only for future nanoelectronics but back-end of line (BEOL) compatible monolithic three-dimensional (M3D) integration recently. For high performance and low power devices, various high-k oxide/Ge gate stacks including ferroelectric oxides have been investigated. Here, we demonstrate atomic layer deposited (ALD) polycrystalline (p-) HfO <sub xmlns:mm...

A one-dimensional model of the polysilicon-gate-oxide-bulk structure is presented in order to analyze the implanted gate MOS-devices. The influence of the ionized impurity concentration in the polysilicon-gate near the oxide and the charge at the polysilicon-oxide interface on the flat-band voltage, threshold voltage, inversion layer charge and the quasi-static C-V characteristic is quantitativ...