In this paper, the design of decimation in time Radix-2 FFT processor is presented, which is integrated in FPGA chip, regarding FPGA as design carrier. New butterfly-shaped operation method is proposed based on the traditional FFT algorithm and the analysis of hardware unit, which can reduce multiplication. And it adopted the Look-up table method .The results of hardware test of FFT processor s...

In the Lagrangian approach to 2-dimensional sigma models, B-fields and D-branes contribute topological terms action of worldsheets both open closed strings. We show that these naturally fit into a 2-dimensional, smooth open-closed functorial field theory (FFT) in sense Atiyah, Segal, Stolz-Teichner. give detailed construction this FFT, based on definition suitable bordism category. category, al...

Graphic Processing Units (GPU) has been proved to be a promising platform to accelerate large size Fast Fourier Transform (FFT) computation. However, current GPU-based FFT implementation only uses GPU to compute, but employs CPU as a mere memory-transfer controller. The computation power in today’s high-performance CPU is wasted. In this project, a hybrid optimization framework is proposed to u...

A novel approach for scalable length Fast Fourier Transform (FFT) in single Processing Element (single PE) architecture has been developed. Scalable length FFT design meets the different lengths requirement of FFT operation in OFDM system [1]. An efficient mechanism that named Interleaved Rotated Data Allocation (IRDA) to replace multiple-port memory with single-port memory has also been propos...

The number of multiplications has been used as a key metrics for comparing FFT algorithms since it has a large impact on the execution time and total power consumption. In this paper, we present a 16-point FFT Butterfly PE, which reduces the multiplicative complexity by using real, constant multiplications. A 1024-point FFT processor has been implemented using 16-point and 4-point Butterfly PEs...

The fast Fourier transform (FFT) processor of the above paper,1 contains many interesting and novel features. However, bit reversed input/output FFT algorithms, matrix transposers, and bit reversers have been noted in the literature. In addition, lower radix algorithms can be modified to be made computationally equivalent to higher radix algorithms. Many FFT ideas, including those of the above ...

In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double proces...