In this paper, various designs of low-power full-adder cell are studied. Simulation of these full-adder cells are carried out. The experiments simulate all combinations of input transitions and consequently determine the power consumption for the various full-adder cells. The simulation results highlight the weaknesses and the strengths of the various full-adder cell designs. The high performan...

In this paper, a full adder cell based on majority function using Carbon-Nanotube Field-Effect Transistor (CNFET) technology is presented. CNFETs possess considerable features that lead to their wide usage in digital circuits design. For the design of the cell input capacitors and inverters are used. These kinds of design method cause a high degree of regularity and simplicity. The proposed des...

This paper presents the design and implementation of a time driven adder generator architecture. There exists a large variety of adders designed to satisfy different computation requirements, in particular we list the Carry Look Ahead (CLA) adder, the skip adder, the ripple adder, the carry select adder (CSA), etc. These different architectures will offer different delays and it is up to the us...

In this paper, a high speed and low power 16x16 Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional adder structures. A Novel technique for digit multiplication namely Vedi...

This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based ...

Micro-electronic devices are playing a very prominent role in electronic equipments which are used in daily life. For electronic equipment battery life is important. So, in order to reduce the power consumption we implement a Sleepy technique to the electronic circuits. Sleepy technique is also called as power gating technique. In the power gating structure, a circuit operates in two different ...

The Wallace Multiplier is mainly used in the Arithmetic & Logic Unit (ALU) to perform the scientific computation in processors, controller etc... The existing multiplication technique like booth multiplier, array multiplier etc requires more time in multiplications. Hence Wallace Multiplier has been designed by using the parallel process to reduce the delay. The regular Wallace Multiplier requi...

the full adders (fas) constitute the essential elements of digital systems, in a sense that they affect the circuit parameters of such systems. with respect to the mosfet restrictions, its replacement by new devices and technologies is inevitable. qca is one of the accomplishments in nanotechnology nominated as the candidate for mosfet replacement. in this article 4 new layouts are presented fo...

Application of logical effort on transistor-level analysis of different 64-bit adder topologies is presented. Logical effort method is used to estimate delay and impact of different adder topologies and to evaluate the validity of the results obtained using logical effort methodology. The tested adder topologies were Carry-Select, Han-Carlson, Kogge-Stone, Ling, and Carry-Lookahead adder. The q...

In this paper, we survey various designs of low-power full-adder cells from conventional CMOS to really inventive XOR-based designs. We further describe simulation experiments that compare the surveyed full-adder cells. The experiments simulate all combinations of input transitions and consequently determine the delay and power consumption for the various full-adder cells. Moreover, the simulat...