In this paper, we propose and evaluate a novel design of a lightly doped drain and source carbon nanotube field effect transistor (LDDS-CNTFET) with a negative differential resistance (NDR) characteristic, called negative differential resistance LDDS-CNTFET (NDR-LDDS-CNTFET). The device was simulated by using a non equilibrium Green’s function method. To achieve this phenomenon, we have created...

To achieve high performance Ge nMOSFETs it is necessary to reduce the metal/semiconductor Schottky barrier heights at the source and drain. Ni/Ge and NiGe/Ge Schottky barriers are fabricated by electrodeposition using n-type Ge substrates. Current (I)–voltage (V) and capacitance (C)–voltage (V) and low temperature I–V measurements are presented. A high-quality Schottky barrier with extremely lo...

In this paper, the EKV3.0 model used for RF analog designs was validated in all-inversion regions under bias conditions and geometrical effects. A conversion of empirical data of 180nm CMOS process to EKV model was proposed. A MATLAB developed algorithm for parameter extraction was set up to evaluate the basic EKV model parameters. Respecting the substrate, and as long as the source and drain v...

Articles you may be interested in Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors Appl. Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide-semiconductor transistors Appl. Effects of gate bias on hot-carrier reliability in drain extended metal-oxide-semiconductor transistors Appl. D...

This article studies the sub-linearity of output characteristics measured in Schottky-barrier metal-oxide-semiconductor field-effect transistors with simulations and experiments. It is shown that not due to forward-biased Schottky diode at drain contact interface but bias impact on source-side Schottky-barrier, resulting an increased carrier injection increasing drain–source voltage. The simula...

Article history: Received 2 February 2016 Received in revised form 10 May 2016 Accepted 16 May 2016 Available online 9 June 2016 Thiswork proposes a numerical charge-based newmodel to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration of a single expression that physically describes the junctionles...

In this paper previous works on calculating the output current of SBCNFET are reviewed and a new three capacitance model for estimating potential profile along the channel is proposed. Furthermore the transmission coefficient through the channel has studied and some new formulas considering the electron coherency in the channel are suggested. Electron coherency will results in resonant transmis...

In the past 30 years, the semiconductor industry has been expanded drastically by the downsizing of the transistors. The progress of the downsizing, however, has increased the chip power. As the battery-powered products, like mobile computers and mobile phones, become popular, the low-power design becomes the one of the most important issues of the LSI design. On the other hand, high-performanc...

In this paper, we have proposed a 2D analytical model for Asymmetric gate stack triple metal MOSFET(AGSTMGAAFET) and performed comparative analysis with the simulation results obtained using SILVACO 3D software. Existing devices such as all around single (SMGAAFET), (TMGAAFET), (GSSMGAAFET), (GSTMGAAFET) asymmetric (AGSTMGAAFET) been compared our structure AGSTMGAAFET. Our device provides excel...