In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as...

Metal–Oxide–Semiconductors In article number 2201110 by Tae-Sik Yoon and coworkers, a tunable multilevel gate oxide capacitance flat-band voltage shift characteristics in double-floating-gate metal-oxidesemiconductor capacitors are demonstrated as operating with both conducting filament formation electrical charging the stack, depending on constituent materials device geometries. It paves way f...

This paper shows that the Surrounding Gate Transistor (SGT) can be scaled down to decananometer gate lengths by using an intrinsically-doped body and gate work function engineering. Strong gate controllability is an essential characteristics of the SGT. However, by using an intrinsically-doped body, the SGT can realize a higher carrier mobility and stronger gate controllability of the silicon b...

In the present paper we have done a comparative analysis of Dual Gate MOSFET having split gate architecture and conventional Dual Gate MOSFET architecture. Simulations have been performed using SILVACO-ATLAS tool, which shows significant improvement in characteristic of split gate architecture in comparison to the conventional structure. The split gate architecture consist two different materia...

A novel 3D field effect transistor on SOI – screen-grid FET (SGrFET) – is proposed and an analysis of its DC behaviour is presented by means of 2D TCAD analysis. The novel feature of the SGrFET is the design of 3D insulated gate cylinders embedded in the SOI body. This novel gate topology improves efficiency and allows great flexibility in device and gate geometry to optimize DC performance. Th...

The relationship of drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, thicknesses top bottom gate oxide films is derived for asymmetric junctionless double (JLDG) MOSFETs. characteristics between the current voltage by using potential distribution model to propose in this paper. In case, threshold defined as corresponding when (W/L) × 10-7 A, DIBL represent...

The micromeres of sea urchin embryos have two functions: to promote the autonomous differentiation of skeletogenic cells and to induce endomesodermal tissues. Micromere specification is controlled by a double-repression gate consisting of two repressors, Pmar1 and HesC. Micro1/pmar1 encodes a transcriptional repressor with a paired-type N-terminal homeodomain and two C-terminal serine-rich repe...

The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed a...