An arithmetic circuit or formula is multilinear if the polynomial computed at each of its wires is multilinear. We give an explicit polynomial f (x1, . . . ,xn) with coefficients in {0,1} such that over any field: 1. f can be computed by a polynomial-size multilinear circuit of depth O(log2 n). 2. Any multilinear formula for f is of size nΩ(logn). This gives a superpolynomial gap between multil...

This paper presents effective design of ternary ALU using Carbon Nano tube Field effect transistor (CNTFET) atv32 nm technology. Ternary logic is possible substitutes to traditional binary logic, because more number operation can performed using ternary logic as compare to binary logic due to this possible to achieve simplicity and energy efficient inrecent digital logic design due to reduced c...

We show that homomorphic evaluation of (wide enough) arithmetic circuits can be accomplished with only polylogarithmic overhead. Namely, we present a construction of fully homomorphic encryption (FHE) schemes that for security parameter λ can evaluate any width-Ω(λ) circuit with t gates in time t · polylog(λ). To get low overhead, we use the recent batch homomorphic evaluation techniques of Sma...

Engineers targeting DSP to FPGAs have traditionally used fixed-point arithmetic, mainly because of the high cost associated with implementing floating-point arithmetic. That cost comes in the form of increased circuit complexity and often degraded maximum clock performance. Certain applications demand the dynamic range offered by floating-point hardware but require speeds and circuit sizes usua...

Using the Vibration signatures obtained during the operations as the original data, a mechanical condition monitoring method for vacuum circuit breaker is developed in this paper. The method combined the time-frequency analysis and the condition recognition based on artificial neural network. During preprocessing, the vibration signature was decomposed into individual frequency bands using the ...

Arithmetic Logic Unit (ALU) is a heart of microprocessor and microcontroller units that are playing main role in digital computers. By optimizing the ALU circuit in microprocessor and microcontroller highly power efficient digital system can be achieved. The use of low power and high performance sub-blocks like adder and multiplier can reduce the total power dissipation of ALU. So in this paper...

Energy recovery technique has attracted interest of low power VLSI designers in recent years. This low power design technique has been proposed and discussed by many researchers. In this paper, we implemented energy recovery technique in the PSPICE using an 8-bit full adder circuit as an example. Full adder circuit has been widely used in arithmetic operations for addition, multipliers and Arit...

The power-delay product is a direct measurement of the energy expanded per operational cycle of an arithmetic circuit. Lowering the supply voltage of the full adder cell to achieve low power-delay product is a sensible approach to improve the power efficiency at sustainable speed of arithmetic circuits composed of such instances at high level design. In this paper, a novel design of a low power...

Squaring and exponentiation of a number are fundamental arithmetic and widely used in the real-time applications such as image processing, digital filtering and cryptography. In this paper, we propose a squaring algorithm of an integer with canonical signed-digit (CSD) number representation. For an n-digit CSD number, our method generates n/4 CSD numbers of 2n-digit length as partial products. ...