The existence of false paths complicates the task of accurate timing analysis significantly. A technique to remove false paths from a combinational circuit without degrading its performance has a practical value since topological timing analysis is then good enough to estimate the performance of false-path-free circuits accurately. One can think of the KMS algorithm [1] as such a procedure. It ...

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in most cases of our expe...

a1 AbstractWe describe an analog VLSI circuit that computes the time delay between an arbitrary input signal and its delayed version. Versions of this circuit will be used as the basic computational elements for human auditory localization models in both the horizontal and vertical directions. Since the circuit uses subthreshold CMOS circuitry, chip measurements show that delays ranging over fi...

The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circui...

In this paper we introduce a VLSI priority encoder that uses a novel priority lookahead scheme to reduce the delay for the worse case operation of the circuit, while maintaining a very low transistor count. The encoder's topmost input request has the highest priority; this priority descends linearly. Two design approaches for the priority encoder are presented, one without a priority lookahead ...

As semiconductor manufacturing entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this paper, we present a model and analysis of NBTI impact on circuit delays. First, we model NBTI impact on gate intrinsic delay and output transition delay. The insights of our models reveal that NBTI...

Power optimization is the major problem in digital circuit design. In this paper using MTCMOS and stack techniques are proposed. Multi threshold CMOS sleep stack and logic stack, super cutoff sleep stack and logic stack are proposed. Stacking is introduced in MTCMOS concept which decreases leakage power based on the power dissipation of pMOS and nMO Stransistor. MTCMOS technique uses multiple v...

Abstract Group velocity superluminal phenomenon, also known as negative group delay or refers to a of envelope signal at the output end medium before input, in time axis, is leave appears entering medium, but this does not violate causality. Based on waveguide theory delay, paper uses transfer function, amplitude response and phase shift electronic circuit control velocity, introduces three fir...