A protocol processor is a programmable processor specifically designed to deal efficiently with protocols. The challenge in designing protocol processors is finding an architecture that is a good compromise between a general purpose processor and a custom, protocol-specific processor. We describe a methodology in which we design both a processor and a program for a network processing applicatio...

With recent advances in AI technology, there has been increased interest in improving AI computational throughput and reducing cost, as evidenced by a number of current projects. To obtain maximum benefit from these efforts, it is necessary to scrutinize possible efficiency improvements at every level, both hardware and software. Custom AI machines, better AI language compilers, and massively p...

Embedded systems are typically designed for one or a few target applications, allowing for customization of the system architecture for the desired system goals such as performance, power and cost. The memory subsystem will continue to present significant bottlenecks in the design of future embedded systems-on-chip. Using advance knowledge of the application’s instruction and data behavior, it ...

This paper outlines a case study at SGS-Thomson Microelec-tronics on the development of a firmware development environment in cooperation with Thomson Consumer Electronics Components. The enviornment is for an embedded processor used for audio decompression algorithms including: MPEG2, Dolby AC-3 Surround, and Dolby Pro-logic. The enabling component of the firmware environment is a retargetable...

Power savings that can be achieved by data-reuse decisions targeting at a custom memory hierarchy for multimedia applications executing on embedded cores are examined in this paper. Exploiting the temporal locality of memory accesses in data-intensive applications a set of data-reuse transformations on a typical motion estimation algorithm is determined. The aim is to reduce data related power ...

This paper reports the result of a comparison between reduced instruction set computing and the transport triggered architecture. Because of the simplicity and efficiency of the transport triggered architecture, its processor requires less execution cycles compared to the OpenRisc processor. This paper also presents a case study about designing an Architecture Definition File for a transport tr...

The concept of a reconfigurable processor comes from the idea of having a general-purpose processor coupled with some reconfigurable resources that allow implementation of custom application-specific instructions. This thesis describes OneChip, a third generation reconfigurable processor architecture that integrates a Reconfigurable Functional Unit (RFU) into a superscalar Reduced Instruction S...

IVRT is an ITS for visual reasoning, using the missing view problem. It combines an ITS framework with a solid modeling kernel that supports hintgenerating rules using geometric reasoning. We develop an ontology for IVRT’s hint generation rules, and a separate ontology for IVRT’s teaching strategy. Teaching strategy rules are stored in a custom text format, with compilation to Jess. The ability...

Pattern-based representation (PBR) is a novel sparse matrix representation that reduces the index overhead for many matrices without zero-filling and without requiring the identification of dense matrix blocks. The PBR analyzer identifies recurring block nonzero patterns, represents the submatrix consisting of all blocks of this pattern in block coordinate format, and generates custom matrix-ve...

PA-RISC is Hewlett-Packard's (HP) reduced instruction set computer (RISC) architecture that is used in its high-performance computer systems (Mahon et al. 1986). Implementations of this architecture have produced some of the most complex processor boards that HP makes (Robinson et al. 1987; Gassman et al. 1987): They can contain as many as 8 very large scale integrated (VLSI) chips—most of them...