The yield of a VLSI chip depends, among other factors, on the sensitivity of the chip to defects occurring during the fabrication process. To predict this sensitivity, one usually needs to compute the so-called critical area (A c) which reeects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate A...

Two algorithms that calculate the critical areas of integrated circuit mask layout for extra material defects are presented. The first algorithm generates a set of edges that define the critical area of the layout for a given defect size. The second algorithm generates the set of fault critical area edges. These identify all possible extra material circuit faults that can occur from a defect of...

Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Euleri...

Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Euleri...

In the past few years, several tools for the automation of the analog integrated circuit (IC) cell and system layout design, with application on both new and reused designs have emerged. Yet, most of the layout design is still handmade, essentially because analog designers want to have total control over the different design options, and also, due to the fact that current fully automated genera...

The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to non equiprobable faults, which are collected from the IC layout, using the information on a typical IC process line defect statistics. The concept of weighted fault coverage is introduced, and the Defect ...

Hromkovif, J., S.A. Loikin, A.I. Rybko, A.A. Sapoienko and N.A. Skalikova, Lower bounds on the area complexity of Boolean circuits, Theoretical Computer Science 97 (1992) 2855300. The layout area of Boolean circuits is considered as a complexity measure of Boolean functions. Introducing the communication complexity of Boolean circuits and proving that this communication complexity squared provi...

The mathematical model and methods of calculation of the layout structure of comparator signal circuits with distributed parameters are presented. The algorithm of computer formulation and solving of equations of transfer functions of comparator circuits is provided. Theoretical substantiation of optimizing the micro-layout of large-scale integration circuits of parallel subnanosecond analog-to...