Decoupling capacitor location in DC power bus design is a critical design choice for which proven guidelines are not well established. The mutual inductance between two closely spaced vias can have a great impact on the coupling between an IC and a decoupling capacitor. This coupling is a function of the spacing between the IC and capacitor, and spacing between power and ground layers. The impa...

In deep submicron CMOS and BICMOS technologies, antenna effects affect floating gate charge of usual floating gate test structures, dedicated to capacitor matching measurement. In this paper a new pseudo-floating gate test structure is designed. After test structure and modeling presentation, testing method and results are given for several capacitor layouts (poly-poly and metal-metal). key wor...

This paper presents the most important multilevel inverter topologies like diode-clamped inverter (neutral-point clamped), capacitor-clamped (flying capacitor), and cascaded multicell( H-Bridge ) with separate dc sources. A Comparison of 5-level hybrid cascaded inverter with PWM method, 5 level diode clamped inverter & 5 level capacitor coupled inverter is also presented in this paper. This pap...

In the present deregulated environment, optimal placement of Distributed Generation (DG) and shunt capacitor in the distribution network plays a vital role in distribution system planning. In this paper, an analytical approach for optimal placement of combined DG and Capacitor units are determined with the objective of power loss reduction and voltage profile improvement. Firstly, the DG unit i...

The performance of D-STATCOM depends on capacitor voltage regulation. In D-STATCOM, the nonlinear controller is preferred to linear controller. Regulating and fixing the capacitor DC voltage in DSTATCOM can improve the system dynamic such as capacitor voltage response, current response and modulation index. The regulation of DC capacitor voltage based on optimal PI co-efficient. In conventional...

Analytic calculations of the electric field of a parallel-plate capacitor are notoriously difficult [1, 2, 3, 4, 5, 6, 7, 8]. The usual goal of such efforts is a calculation of the correction to the hard-edge approximation, C = A/4πd (in Gaussian units), of the capacitance for plates of area A separated by distance d. Calculate instead the electromagnetic momentum of the parallel-plate capacito...

This paper presents the analysis of single Miller capacitor feedforward compensation scheme which is used in threestage CMOS operational amplifiers. single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Feed forward technique is effectively combined...

Capacitor-couple technique used to lower snapbacktrigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-coup...