In this paper, a new BIST(Built-In Self-Test) structure for efficient test of embedded RAMs is proposed. In proposed embedded memory BIST(EMBIST) architecture, various algorithms are allowed to be executed, and just one controller can test more than one embedded memories. And, the proposed EMBIST has efficient structure that requires smaller hardware overhead. The experimental result demonstrat...

High-level test synthesis (HLTS) methodologies have attracted much many research interest in recent years as digital design has moved to higher levels of abstraction. Conditional statements in behavioral descriptions tend to produce testability problems and have to be taken care of in the early stage of the design cycle. In this paper, we present an HLTS methodology for the Built-In Self-Test (...

We evaluate some previously proposed test approaches for various types of adders in an attempt to find an architecture-independent algorithm for testing adders in embedded Digital Signal Processors (DSPs) in Field Programmable Gate Arrays (FPGAs). We find that a minor modification to a previously proposed Built-In Self-Test (BIST) approach provides the highest fault coverage for most types of a...

In this paper a method to obtain harmonic transfer matrices (HTM) from simulated or measured values (signature & signature response) is presented. These matrices subserve a description of complex systems (e.g. RF front-ends) with real properties, which can’t be specified by simple analytic expressions. They afford to give statements about a systems parameter. That’s why HTM are suitable for Bui...

In this paper, we present the design and experimental evaluation of an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generatox Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly a...

Concurrent checkers are commonly used in computer systems to detect computational errors on-line, which enhances reliability. Using the coding theory framework developed earlier by the authors, it is shown in the following that concurrent checkers, already available within the circuit, can be utilized very effectively during off-line testing. Specifically, test time as well as fault escape prob...

Partial reset has been shown to have significant impact on deterministic test generation for sequential circuits. In this paper, we explore the use of partial reset in fault-independent testing and application to built-in selftest. We take the following approach: based on fault propagation analysis, we select a subset of the circuit flip-flops to be initialized to 0 or 1. The initialization (se...

A practical approach to generate on-chip precise and slow analog ramps, intended for time-domain analog testing, monotonicity and histogram-based tests of ADCs is proposed. The technique uses an analog discrete-time adaptive scheme to calibrate the ramp generator. The lowest slope is 0.4 V/ms. Three implementations are presented for different levels of accuracy and complexity. Measurement resul...

In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The propos...

We present stuck-at and bridging fault simulation results for previously proposed Built-In Self-Test (BIST) approaches for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs). In addition, new BIST approaches are proposed and analyzed via fault simulation. The fault simulation results are used to compare and evaluate the fault detection capabilities and effectivene...