Information theory provides tools and techniques to measure the fundamental limits of predictability. Apart from this formal basis, researchers have attempted to construct so-called ‘optimal’ predictors in order to conduct limits studies for different aspects of program predictability (such as branch outcomes and method return values). This paper reports on two case studies for branch predictio...

Advanced processors can simultaneously execute multiple instructions in parallel to achieve performance. Branches introduce control dependence between instructions. Branch prediction therefore is important to modern processors. Most present predictors use branch history to predict branch outcomes. Using branch history alone results in delay for identifying mispredictions. In this paper, a conte...

A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. This paper presents a novel cost-eeective mechanism called the two-block ahead branch predictor. Information from the current instruction block is not used for predicting the address of the next instruction block, but rather for predicting the block following the next...

In a typical machine learning classification task there are two phases: training and prediction. This paper focuses on improving the efficiency of the prediction phase. When the number of classes is low, linear search among the classes is an efficient way to find the most likely class. However, when the number of classes is high, linear search is inefficient. For example, some applications such...

One of the key factors determining computer performance is the degree to which the implementation can take advantage of instruction-level parallelism. Perhaps the most critical limit to this parallelism is the presence of conditional branches that determine which instructions need to be executed next. To increase parallelism, several authors have suggested ways of predicting the direction of co...

Looking at trends in recent publications on computer architecture we find that there has been a steep decline in the number of published works relating to branch prediction. Further inspection reveals that while older trends include development of new predictor designs [12][15][8][10], more modern trends have been favoring the consumption of larger history and storage to attain better hit rates...

Unlike traditional superscalar processors, Simultaneous Multithreaded processor can explore both instruction level parallelism and thread level parallelism at the same time. With a same fetch width, SMT fetches instructions from a single thread not so deeply as in traditional superscalar processor. Meanwhile, all the instructions from different threads share the same Function Unites in SMT. All...

To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundamental limit to improving ILP is data dependences among instructions. If data dependence information is available at run-time, there are many uses to improve ILP. Prior published examples include decoupled branch execution...

Abstract. Java programs are increasing in popularity and prevalence on numerous platforms, including high-performance general-purpose processors. The dynamic characteristics of the Java runtime system present unique performance challenges for several aspects of microarchitecture design. In this work, we focus on the effects of indirect branches on branch target address prediction performance. R...

In our previous published research we discovered some very difficult to predict branches, called unbiased branches that have a “random” dynamical behavior. We developed some improved state of the art branch predictors to predict successfully unbiased branches. Even these powerful predictors obtained very modest average prediction accuracies on the unbiased branches while their global average pr...