This paper examines the bit and power allocation problem for orthogonal frequency division multiplexing systems in which the overall transmission power is minimized by constraining the fixed data rate and bit error rate. To provide the optimal allocation with less computational complexity, we propose new bit and power allocation schemes based on the Lagrangian method. Firstly, we propose an ini...

This paper presents low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed names as Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these mu...

The main objective of this paper is to provide a solution for VLSI designers to design configurable Booth Multiplier that supports single 4-bit, single 8-bit, single 12-bit or single 16-bit multiplication. Multiplication is one of the basic functions used in digital signal processing for computation. Therefore, we need efficient algorithms to reduce the computations. Hence in order to minimize ...

A methodology for designing processor architectures oriented to matrix-vector operations is proposed in this paper. The methodology is based on high-radix multiplication where first a list of potential partial products (PPs) of one operand with all possible t-bit numbers (t ∈ {2, 3, 4}) are computed by simple shifts and additions, then selected PPs from this list are shifted and added according...

This paper sets speed records on well-known Intel chips for the Curve25519 ellipticcurve Diffie-Hellman scheme and the Ed25519 digital signature scheme. In particular, it takes only 159 128 Sandy Bridge cycles or 156 995 Ivy Bridge cycles to compute a Diffie-Hellman shared secret, while the previous records are 194 036 Sandy Bridge cycles or 182 708 Ivy Bridge cycles. There have been many paper...

Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)-based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technolog...

An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-powered intelligent wireless sensor network systems. To address this issue, we present a reconfigurable power-aware scalable Booth multiplier designed to provide low power consumption for DSP applications in highly changing environm...

We propose both adder and multiplier circuits for bitstream signal processing customized for tri-level sigma–delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy.