Fault diagnosis is important in improving the design process and the manufacturing yield of nanometer circuits. It is however a challenging problem as today’s complex defects lead to an explosion of the diagnosis solution space with the increasing number of possible fault locations and fault models. Our goal in this study consists in developing a new diagnosis method targeting almost all the na...

This paper provides a new approach for object-oriented reengineering. One of the difficulty in software testing and maintenance has been identified as caused by the convention that code and its tests are developed and described separately. This paper develops a method of built-in test (BIT) for OO reengineering. The advantage of this method is that the BITs in reengineered OO software (OOS) can...

The number of embedded cores in an FPGA has been increasing and different devices use different numbers of different types of hard IP cores. To facilitate failure analysis and reduce its turnaround time, we present an automated BIST-based methodology that exploits the existing redundant resources of an FPGA and its reconfigurabilty to efficiently locate the faulty IP block(s) in addition to pas...

With the upcoming trend towards built-in test structures and implicit testing, more and more issues of test design need to be resolved during circuit design. A basic requirement for manual as well as for automatic test generation is to assess how accurately a given test strategy will classify good and faulty circuits. Measurement error plays an important role here and must be taken into account...

We present a new technique for uniquely identifying a single failing vector in an interval of test vectors. This technique is applicable to combinational circuits and for scan-BIST in sequential circuits with multiple scan chains. The proposed method relies on the linearity properties of the MISR and on the use of two test sequences, which are both applied to the circuit under test. The second ...

This paper presents a Built-In-Self-Test (BIST) implementation of pseudo-random testing for MEMS. The technique is based on Impulse Response (IR) evaluation using pseudo-random Maximum–Length Sequences (MLS). We will demonstrate the use of this technique for an on-chip fast and accurate broadband determination of MEMS behaviour, in particular for the characterisation of MEMS structures such as ...

This paper discusses the viability of a BIST implementation for the sinusoidal histogram technique classically used for ADC testing. An original approach based on (i) approximations to estimate the ADC parameters, (ii) decomposition of the global test in a code-after-code test procedure and (iii) piece-wise approximation to compute the ideal histogram is developed. These three features allow a ...

In real-time systems, dynamic inconsistencies of software are hardly detected, diagnosed and handled. A built-in test (BIT) method is developed to cope with software dynamic inconsistency. BIT is defined as a new kind of software testing which is explicitly described in object-oriented source code as member functions. BITs can be activated at any designed moment at run-time to detect, diagnose ...

In this chapter we give an overview of digital testing techniques with appropriate reference to material containing all details of the methodologies and algorithms. First, we present a general introduction of terminology, a taxonomy of testing methods and of fault models. Then we discuss the main approaches for the generation of test patterns, both algorithmically and pseudo-randomly, concludin...

In this paper, the authors propose a new transparent built-in self-test method to test in parallel multiple embedded memory arrays with various sizes. First, a new transparent test interface is designed to perform testing in the normal mode and to cope with test interrupts in a real-time manner. The circular scan test interface facilitates the processes of both test pattern generation and signa...