This paper addresses the problem of synthesizing an asynchronous system from a temporal specification. We show that the cost of synthesizing a single-process implementation is the same for synchronous and asynchronous systems (2EXPTIME-complete for CTL* and EXPTIME-complete for the μ-calculus) if we assume a full scheduler (i.e., a scheduler that allows every possible scheduling), and exponenti...

A framework for evaluating the performance of asynchronous systems is presented. Performance evaluation of the asynchronous circuits is a challenging process due to the dependencies between highly concurrent events. The utilized performance model is a Probabilistic Timed Petri-Net (PTPN) with possible choice places to capture the conditional behavior of the system. The proposed framework exploi...

There are several methods of describing systems in a modular fashion. These descriptions may represent a system in one of several ways, for example in a text form or as a graph. By using a modular representation, a large system can be split into multiple smaller sections, which can make operations such as verification of a system simpler and quicker. Multiple methods of designing asynchronous c...

The asynchronous systems are the non-deterministic models of the asynchronous circuits from the digital electrical engineering, where non-determinism is a consequence of the fact that modelling is made in the presence of unknown and variable parameters. Such a system is a multi-valued function f that assigns to an (admissible) input u : R! f0; 1gm a set f(u) of (possible) states x : R! f0; 1gn:...

This paper addresses an alternative approach to detecting the completion of computation in asynchronous digital circuits. Presented method, as the name suggests, is based on sensing the amount of current drawn by the combinatorial logic and exploits the behavior of CMOS logic gates for separating the computation state from the idle state. The paper deals with the current sensor design, its impl...

Based on PAFAS (Process Algebra for Faster Asynchronous Systems), a testing-based fasterthan relation has previously been developed that compares the worst-case efficiency of asynchronous systems. This approach reveals that pipelining does not improve efficiency in general; that it does so in practice depends on assumptions about the user behaviour. As a case study for testing under such assump...

Silicon technologies advances brought the possibility of integrating billions of transistors in a VLSI die. However, as these transistors become smaller due to fabrication method enhancements, some aspects that were negligible in older technologies emerge as difficulties for the design in current and future technology nodes. In this context, fully synchronous digital circuits become harder to b...

The mass application of asynchronous design has been an elusive goal for academic researchers while recent advances are promising. However asynchronous circuit has some inherent advantages over synchronous counterpart. The matrix – vector multiplication core of discrete cosine transforms (DCT) is demonstrated in this paper, by non linear pipelined templates. From this proposed DCT applications,...

The roadblock to wide acceptance of asynchronous methodology is poor CAD support. Current asynchronous design tools require a significant re-education of designers, and their capabilities are far behind synchronous commercial tools. This paper considers the testing methodology for a particular subclass of asynchronous circuits (Null Convention Logic or NCL) that entirely relies on conventional ...