-In this paper, area-efficient architectures for the implementation of integer discrete cosine transform (DCT) of different lengths to be used in High Efficiency Video Coding (HEVC) are proposed. An efficient constant matrix multiplication scheme can be used to derive parallel architectures for 1-D integer DCT of different lengths such as 4, 8, 16, and 32. Also power-efficient structures for fo...

The evaluation of leaf area is required in several agronomic studies given their importance to assess the plant growth. The objective of this study was to use statistical models to estimate leaf area of five clonal varieties of coffee (Coffea canephora) from linear dimensions (length and width maximum). Were used in the studies five varieties of Coffea canephora Pierre ex Froehner: Emcapa 8111,...

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed.  This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage ...

The study of sum-product phenomena and product phenomena is an emerging research direction in combinatorial number theory that has already produced several striking results. Many related problems are not yet fully understood, or are far from being resolved. In what follows we propose several questions where progress can be expected and should lead to advances in this general area. For two finit...

In determining whether a plant that is the product of gene editing would be regulated in Canada, it is important to consider whether the product would be considered to be novel. The following discussion will focus on Canada’s product-based approach to assessing plants with novel traits (PNTs) for use as food, as feed, and for release into the Canadian environment. As the author works in the are...

In this paper, we develop generalized methods to layout homogeneous product networks with any number of dimensions, and analyze their VLSI complexity by deriving upper and lower bounds on the area and maximum wire length. In the literature, lower bounds are generally obtained by computing lower bounds on the bisection width or the crossing number of the network being laid out. In this paper, we...

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