Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of convolution codes, at the receiver end Viterbi Decoder is being employed. The parameters of Viterbi algorithm can be changed to suit a specific application. The high speed and small area are two important design parameter...

In today’s digital communication systems, Convolutional codes are broadly used in channel coding techniques. The Viterbi decoder due to its high performance is commonly used for decoding the convolution codes. Fast developments in the communication field have created a rising demand for high speed and low power Viterbi decoders with long battery life, low power dissipation and low weight. Despi...

Efficient convolutional coding and decoding algorithms are most crucial to successful operation of wireless communication systems in order to achieve high quality of service by reducing the overall bit error rate performance. A widely applied and well evaluated scheme for error correction purposes is well known as Viterbi algorithm [7]. Although the Viterbi algorithm has very good error correct...

Delft University of Technology Faculty of Electrical Engineering, Mathematics and Computer Science CE-MS-2003-13 Entropy Decoding is an essentially sequential task. Executing this task on a processor that benefits from Instruction Level Parallelism (ILP), Data Level Parallelism (DLP) or both requires an efficient implementation of Entropy Decoding. Entropy Decoding forms the part of MPEG-2 Deco...

Since its introduction in 1993, the turbo coding error-correction technique has generated a tremendous interest due to its near Shannon-limit performance. Two key innovations of turbo codes are parallel concatenated encoding and iterative decoding. In its IMT-2000 initiative, the International Telecommunication Union (ITU) adopted turbo coding as a channel coding standard for Third-Generation (...

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with t...

In this paper we present the concept of a high-throughput multi-mode channel decoder architecture that consists of a tightly coupled array of independently programmable processing cores. Every core is capable of decoding low-density parity-check (LDPC), convolutional turbo (CTC) and convolutional codes (CC) either independently or jointly with other cores. This approach allows parallel handling...

The multiplication of connected devices goes along with a large variety of applications and traffic types needing diverse requirements. Accompanying this connectivity evolution, the last years have seen considerable evolutions of wireless communication standards in the domain of mobile telephone networks, local/wide wireless area networks, and Digital Video Broadcasting (DVB). In this context, ...

A high-speed real-time decoder for t-errorcorrecting binary Bose-Chaudhuri-Hocquenghem (BCH) codes based on a modified step-by-step decoding algorithm is presented. The average operation cycles for decoding each received word is just equal to the block length of the codeword. The decoder is constructed by three modules: the syndrome module, the comparison module, and the error corrector. Since ...

This paper presents a novel forward-backward four-way merger min-max algorithm and high-throughput decoder architecture for nonbinary low-density parity-check (NB-LDPC) decoding, which significantly reduces decoding latency. An efficient partial-parallel block-layered decoder architecture suitable for the proposed forward-backward four-way merger algorithm is presented to speed up the decoder c...