fault tree analysis (fta) as a probabilistic risk assessment (pra) method is used to identify basic causes leading to an undesired event, to represent logical relation of these basic causes in leading to the event, and finally to calculate the probability of occurrence of this event. to conduct a quantitative fta, one needs a fault tree along with failure data of the basic events (bes). someti...

BACKGROUND AND PURPOSE A noninvasive investigation with high spatial resolution and without metal artifacts is necessary for long-term imaging follow-up after flow-diverter implantation. We aimed to evaluate the diagnostic value of conebeam CT angiography with intravenous contrast enhancement in the assessment of vascular status following implantation of the Pipeline Embolization Device and to ...

Transportation of unrefined crude oil from the production unit to a refinery or large storage area by a pipeline is difficult due to the different properties of crude in various areas. Thus, the design of a crude oil pipeline is a very complex and time consuming process, when considering all the various parameters. There were three very important parameters that play a significant role in the t...

Pipeline FFT processors are used in mobile communication systems and in particular in OFDM-based systems. This paper presents a method for power analysis and clock optimization of pipeline FFT processors for particular OFDM baseband system. This method is applied to various architectures with different radices. The analysis can be used in the design of high speed pipeline FFT processors.

The pipeline processor is a common paradigm for very high speed computing machinery. Pipeline processors provide high speed because their separate stages can operate concurrently, much as different people on a manufacturing assembly line work concurrently on material passing down the line. Although the concurrency of pipeline processors makes their design a demanding task, they can be found in ...

Micro-threads are small fragments of code based on loops, can be executed concurrently and the concurrency is described parametrically in the binary code. This thesis describes a microthreaded model of concurrency and illustrates the complete bottom-level design of its pipeline compared with the conventional MIPS pipeline. The simulations from a single microthreaded processor implemented in VHD...

Pipeline morphing is a simple but e ective technique for recon guring pipelined FPGA designs at run time. By overlapping computation and recon guration, the latency associated with emptying and re lling a pipeline can be avoided. We show how morphing can be applied to linear and mesh pipelines at both word-level and bit-level, and explain how this method can be implemented using Xilinx 6200 FPG...

A new class of latch controllers for asynchronous pipelines is presented. In addition to the standard operating mode, they can be configured in a collapsed mode, where the pipeline latches they control are kept transparent effectively joining the neighbouring pipeline stages into one. The depth of the resulting pipeline is dynamically adaptable, which can be used for power management of asynchr...