The scaling of CMOS transistors has driven the tremendous growth of the semiconductor industry for the last four decades. However, most experts are saying CMOS is reaching its limits. This paper discusses the technologies that may postponing the scaling limit and the technologies that may replace CMOS when the limit is reached.

In the past Smart Power System-on-Chip (SoC) products were almost exclusively designed on Bipolar-CMOS-DMOS (BCD) technologies. These products address applications as diverse as power management for mobile phones, motor drivers, printer head drivers, automotive bus transceivers and dataline drivers for high speed internet or Voice over IP (VoIP). The trend towards SoC design for lowering form f...

We have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors. As the circuit elements, a fully-depleted-silicon-on-insulator (FD-SOI) CMOS process was adopted because they keep good static performance even at 4.2 K where where various anomalous behaviors are seen for other types of CMOS transistors. We have designed and fabricated sever...

Emerging non-volatile memory (NVM), or memristive, devices promise energy-efficient realization of deep learning, when efficiently integrated with mixed-signal integrated circuits on a CMOS substrate. Even though several algorithmic challenges need to be addressed to turn the vision of memristive Neuromorphic Systems-on-a-Chip (NeuSoCs) into reality, issues at the device and circuit interface n...

Domino logic is a CMOS-based evolution of the dynamic logic techniques. It allows a rail-to-rail logic swing. It was developed to speed up circuits. In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinatorial logic circuits, particularly those implemented in MOS technology. This work is oriented towards implementing the domino logic circuits...

Future technologies required nano-scale CMOS memory to be operating in low power consumption. The minimum operating voltage of the nano-scale CMOS played as a main factor to reduce the power consumption. Consequently, there are some limitations and obstacles to achieve the objective for several design, material and novel structural solutions, which are promising and reliable. In this research, ...

Conventional CMOS technology's performance deteriorates due to increased short channel effects. Double-gate (DG) FinFETs has better short channel effects performance compared to the conventional CMOS and stimulates technology scaling. The main drawback of using CMOS transistors are high power consumption and high leakage current. Fin-type field-effect transistors (FinFETs) are promising substit...

The e!ect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive}capacitive interconnect lines is presented in this paper for di!erent signal combinations. Analytical expressions characterizing the output voltage and the propagation dela...

This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic lo...

CMOS faces new device and technology challenges: MOSFETs require ultra-sharp doping profiles and complex processing; integration of devices into circuits requires arbitrary interconnection with overlay precision beyond known manufacturing solutions (3σ=±3nm, 16nm CMOS, ITRS’11[1]). To overcome these challenges, we propose a new nanoscale computing fabric with integrated design of device, interc...