This document describes the use of the FPGA coprocessor microEnable as Read Out Buffer (ROB) hardware for the trigger system of the Atlas detector. It shows with performance measurements the possibilities of FPGA hardware to buffer and manipulate data received from the detector very fast. It points out that FPGA hardware can be used successfully in the Atlas trigger environment.

This paper presents the architecture and implementation of a real time adaptive NLMS filter for nonstationary noise cancellation in a car environment.The active noise control techniques using adaptive digital filters are very much suitable and well proven.The proposed efficient Adaptive Noise Canceller is realized using Xilinx System Generator 12.3 on Spartan 3E FPGA. System Generator is a DSP ...

734 The JPEG standard is most widely used method of lossy compression for digital photography. In this paper, we will discuss the implementation of JPEG Encoder for FPGAs. The target device is a Stratix IV FPGA. The JPEG Encoder was synthesized and simulated using the Quartus FPGA design software at the clock frequency of 122.5 MHz. The design was tested on an image for different values of the ...

Existing FPGA architectures can be classified along two dimensions: reprogrammable vs. one-time programmable and general-purpose vs. domain specific. The most challenging class of FPGA architectures to design is the reprogrammable, general-purpose FPGA, of which Xilinx is the most wellknown example. In this paper we describe Triptych, a new FPGA architecture that addresses two problems of curre...

This document describes the evaluation of a 200MHz analogue-to-digital converter acquisition evaluation board. The evaluation board contains an AD9410 10-bit ADC [1], which was purchased from Analog Devices for $200. The evaluation board is interfaced via an Altera APEX FPGA to a custom capture card [2]. The APEX FPGA currently contains minimal logic for synchronizing the two data streams from ...

A Dynamic Instruction Set Computer (DISC) has been developed to support demand-driven instruction set mod-iication. Using partial reconnguration, DISC pages instruction modules in and out of an FPGA as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-speci...

In this paper, we describe an FPGA H.264/AVC encoder architecture performing at real-time. To reduce the critical path length and to increase throughput, the encoder uses a parallel and pipeline architecture and all modules have been optimized with respect the area cost. Our design is described in VHDL and synthesized to Altera Stratix III FPGA. The throughput of the FPGA architecture reaches a...

Physical Unclonable Functions (PUFs) provide a secure, power efficient and non-volatile means of chip identification. These are analogous to one-way functions that are easy to create but impossible to duplicate. They offer solutions to many of the FPGA (Field Programmable Gate Array) issues like intellectual property, chip authentication, cryptographic key generation and trusted computing. More...

Although the new generations of FPGAs provide support for partial and dynamic configuration, the huge reconfiguration latency is still a major shortcoming of the current FCCMs . Software and hardware techniques (compiler optimizations, configuration prefetching) have been used in order to reduce the impact of the configuration overhead on the overall performance. Nevertheless, these techniques ...

Welcome to the special issue on field programmable gate arrays (FPGAs). FPGAs are becoming an increasingly important part of embedded systems, as the collection of papers in this issue illustrates. " An overview of reconfigurable hardware in embedded systems " provides a comprehensive overview of the state-of-the-art use of reconfigurable hardware in embedded systems. A detailed discussion of t...