نتایج جستجو برای: حافظه sram
تعداد نتایج: 6868 فیلتر نتایج به سال:
This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM counterparts. This design can be used as cache memory in processors and lowpower portable devices. The proposed SRAM cell features ~13% area reduction compared...
This paper evaluates six different types of interprocedural pointer analyses on 22 telecommunication and media applications and describes their application to an SRAM power reduction technique. This configurable SRAM provides differentiation of data access time and port counts within a single on-chip structure. Scheduling for configurable SRAM relies on inter-procedural dependence analysis for ...
In this paper a Super-Fast Low-Power (SFLP) static random access memory (SRAM) cell has been proposed. The SFLP cell contains two tail transistors in the pull-down path of the respective inverter to minimize the write power consumption The cell is simulated in terms of speed, power and read stability. The simulated results show that the read and write power of the proposed cell is reduced up to...
An SoC with ARM® CortexTM-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted ChannelTM (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via VDD scaling and body biasing. Alternatively, DDC technology demonstrates 35% speed increase at matched power. The results hold across proc...
In this paper, the impact of RDF on the static noise margin (SNM) and read current margin (SINM) of a prototype 22nm 6T SRAM was investigated using TCAD modeling. Individual device statistics of threshold voltages (Vt) and transport related parameters were first extracted for NFETs and PFETs. SNM and SINM characteristics of the corresponding SRAM cells were then analyzed. Two methods to emulate...
In this paper a new SRAM cell is designed with a body bias controller to control leakage, speed and stability. A novel controller circuit is proposed to control the value of threshold voltage. Operation of the proposed controller is based on word line signal levels. In order to reduce sub threshold leakage current, the NMOS access and driver transistor is adjusted to a higher threshold voltage....
This paper presents a CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. The new cell size is 35.45% smaller than a conventional sixtransistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform...
A highly stable 8T SRAM cell is presented to improve the Static Noise Margin (SNM). The proposed 8T SRAM cell uses a single-bit line structure to perform read and write operation. The design enhances the write ability by breaking-up the feedback loop of the inverter pair. It also improves the read stability by eliminating the effects from the bit-line. The simulations show that the proposed 8T ...
In this study, we propose a lightweight and low-latency advanced encryption standard (AES) accelerator. Instead of being connected to the bus through its own slave wrapper, proposed AES accelerator is located within wrapper static random-access memory (SRAM) directly attached SRAM. Hence, can access data in SRAM share space for storing expanded keys, resulting no time transferring input output ...
Thangamani.V Kalaignar Karunanidhi Institute of Technology, Chennai Anna University, Kannampalayam(PO),Coimbatore-641402,TamilNadu,India. Contact No.:8675802322, E-mail: [email protected] Abstract The computer memory system has both volatile and non volatile memory. The Volatile memories such as SRAM and DRAM used as a main memory and non volatile memory like flash memory. But in recent days...
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