* This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education, Science and Technology(2010-0021897). Abstract As the power dissipation has become one of the critical design challenges in a sensor network environment, nonvolatile memories such as STT-MRAM and flash memory will be used in the next generat...

The analyse of the windows based Input and Output workload is driven by various trace captured from running systems for various standard file system benchmarks. To find that many of the issues arise in SSD design appeared in the memory stack. To solving these difficult problems, there is considerable scope for design choice. The following issues are relevant to SSD performance are Data placemen...

We explore the idea of heterogeneous NAND flash which possesses pages/blocks of multiple sizes. This heterogeneity can then be exploited to accommodate the diversity in data access patterns found in most storage workloads. We identify various tradeoffs offered by such pages/blocks. By characterizing seven real-world I/O traces, we identify metrics that have a bearing on the efficacy as well as ...

Flash memories are in ubiquitous use for storage on sensor nodes, mobile devices, and enterprise servers. However, they present significant challenges in designing tree indexes due to their fundamentally different read and write characteristics in comparison to magnetic disks. In this paper, we present the Lazy-Adaptive Tree (LATree), a novel index structure that is designed to improve performa...

Flash translation layer (FTL) is generally used for NAND flash memory in order to handle the mapping between logical page address and physical page address. Log buffer-based FTLs provide good performances with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping architecture between data block and log block, called associativit...

There are various approaches for reducing Flash access time. NOR Flash enables high speed read access at the cost of a twofold density reduction than NAND and a lower program speed [1]. Throughput improvements include cache read and program [2], but those are efficient for sequential access whereas access patterns can be random [3]. Device approaches include program pulse magnitude optimization...

Nowadays, forensic on flash memories has drawn much attention. In this paper, a recovery method for SQLite database history records (I.e. updated and deleted records) form YAFFS2 is proposed. Based on the out-of-place-write strategies in NAND flash memory required by YAFFS2, the SQLite history recorders can be recovered and ordered into timeline by their timestamps. The experiment results show ...

endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness ...

Flash memory based Solid State Drives (SSD) acquiring greater attention in enterprise storage computing environment; this is primarily due to its high I/O speed. SSDs use multiple NAND flash memory chips as a storage media and deploy internal RAM to maintain the flash translation layer (FTL) mapping table. The rest portion of the inner RAM is used as a buffer. This buffer absorbs the write requ...