In this paper, we describe an FPGA H.264/AVC encoder architecture performing at real-time. To reduce the critical path length and to increase throughput, the encoder uses a parallel and pipeline architecture and all modules have been optimized with respect the area cost. Our design is described in VHDL and synthesized to Altera Stratix III FPGA. The throughput of the FPGA architecture reaches a...

Physical Unclonable Functions (PUFs) provide a secure, power efficient and non-volatile means of chip identification. These are analogous to one-way functions that are easy to create but impossible to duplicate. They offer solutions to many of the FPGA (Field Programmable Gate Array) issues like intellectual property, chip authentication, cryptographic key generation and trusted computing. More...

Although the new generations of FPGAs provide support for partial and dynamic configuration, the huge reconfiguration latency is still a major shortcoming of the current FCCMs . Software and hardware techniques (compiler optimizations, configuration prefetching) have been used in order to reduce the impact of the configuration overhead on the overall performance. Nevertheless, these techniques ...

Welcome to the special issue on field programmable gate arrays (FPGAs). FPGAs are becoming an increasingly important part of embedded systems, as the collection of papers in this issue illustrates. " An overview of reconfigurable hardware in embedded systems " provides a comprehensive overview of the state-of-the-art use of reconfigurable hardware in embedded systems. A detailed discussion of t...

Boolean-based routing methods transform the geometric FPGA routing task into a large but atomic Boolean function with the property that any assignment of input variables that satisfies the function specifies a valid routing solution. Previous attempts at FPGA routing using Boolean methods were based on binary decision diagrams which limited their scopes, because of size limitations, to only ind...

The methodology for the design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into the SRAM-based FPGA. The methodology includes detection ...

All rights reserved by www.ijsrd.com 535 FPGA to PC Ethernet Communication using Media Independent Interface (MII) Mode Preeti Kumari Sidharth Kashyap Ajit Jain Lokesh Sharma Department of Electronics Engineering CDAC Noida, GGSIPU Delhi Abstract— As the advancement in the embedded system technology, Field programmable gate array (FPGA) based systems are playing significant role. In many applic...

This paper aims at demonstrating the whole process allowing implementing a robust in-system update solution for Microblaze-based embedded systems using low-cost and low-power consuming Spartan-6 FPGA. In this work, we design a run-time full reconfigurable embedded platform based on the Spartan-6 Multiboot and fallback features. The FPGA Multiboot feature enables switching between two or more co...

ÐThe speed of arithmetic calculations in configurable hardware is limited by carry propagation, even with the dedicated hardware found in recent FPGAs. This paper proposes and evaluates an approach called delayed addition that reduces the carrypropagation bottleneck and improves the performance of arithmetic calculations. Our approach employs the idea used in Wallace trees to store the results ...

Las Funciones Físicamente No-Clonables (PUF) basadas en osciladores de anillo (RO-PUF) son una las implementaciones PUF FPGA más utilizadas actualmente. Sin embargo, la arquitectura afecta a aleatoriedad respuesta. En este trabajo, proponemos algunas formas optimizar RO-PUF implementada FPGA.