Hardware/Software systems nd an ever increasing market. The modeling, partitioning, (co-)simulation and synthesis of such systems requires a uniform language of description for hardware and software on all levels of design. This article presents such a language in form of Java. The article concentrates on the qualiication for modeling and simulation of this language with respect to hardware. It...

A thorough description of the evolving MIMIC Hardware Description Language (MHDL) is presented from the perspective of an analog modeler or designer. Analog simulation issues pertinent to MHDL description are discussed. This includes both transient and steady-state simulation.perspectives. Several modeling examples demonstrate the concepts and simulation issues related to these examples, as wel...

Behavioral speciications in VHDL contain multiple communicating processes. Register level designs synthesized from these speciications contain a data path represented as a netlist and a controller consisting of multiple communicating synchronous nite state machines. These nite state machines together implement the control ow speciied in and implied by the behavioral speciication in VHDL. This p...

Implementing an algorithm to hardware platforms is generally not an easy task. The algorithm, typically described in a high-level specification language, must be translated to a low-level HDL language. The difference between models of computation (sequential versus fine-grained parallel) limits the efficiency of automatic translation. On the other hand, manual implementation is time-consuming, ...

A Variable Node Processing Unit (VNPU) and a Check Node Processing Unit (CNPU) are designed in order to be used in Low Density Parity Check (LDPC) decoding by the Min-Sum Algorithm (MSA). The designed blocks are fully parallel and flexible to be used for different block length when a regular (3, 6) LDPC codes are required. The proposed VNPU and CNPU have been first designed and implemented in s...

This paper describes hardware/software codesign method of the extendible embedded RISC core VIRGO, which based on MIPS-I instruction set architecture. VIRGO is described by Verilog hardware description language that has five-stage pipeline with shared 32-bit cache/memory interface, and it is controlled by distributed control scheme. Every pipeline stage has one small controller, which controls ...

Application Specific Instruction Processors (ASIPs) provide enhanced performance by directly implementing application segments in hardware as custom instructions. Recent work [1, 2] automates generation of custom instructions from application source code. Speedups of up to 6 times [3] are attainable for certain benchmarks. However, instructions generated from C are often restricted to small clu...

Hardware description languages and tools require a considerable amount of teaching activities in digital systems design course, which is difficult to accommodate limited time frame, use for e-learning. This paper presents our user-friendly open-source web-based tool, SHDL, used describe simulate hardware components translate them into standard language. SHDL language tool design, aims improve t...

The GRASP (Graphical Representations of Algorithms, Structures, and Processes) project, which has successfully prototyped a new algorithmic-level graphical representation for software—the control structure diagram (CSD)—is currently focused on the generation of a new fine-grained complexity metric called the complexity profile graph (CPG). The primary impetus for creation and refinement of the ...

Proposed FPGA based technique considers a message as a binary string on which ROBAST is applied. A block of n-bits is taken as an input stream, where n ranges from 8 to 256 – bit, then ROBAST is applied in each block to generate intermediate stream, any one intermediate stream is considered as a cipher text. The same operation is performed repeatedly on various block sizes. It is a kind of bloc...