The floorplan of a VLSI chip and its projected yield are usually considered to be completely unrelated issues. This commonly used assumption does not necessarily hold for seueml recently designed VLSI chips that incorpomte some defect tolemnce. The purpose of this paper is to investigate the relationship betweenfloorplanning and yield for this type of chips.

A new class of non-totally symmetric functions which can be represented as simple regular symmetric arrays without redundancy is identified. Regular circuits are becoming crucialy important for deep submicron technologies, which needs new layout approaches to fully utilized their potential. The new class of functions contains the classes of totally symmetric and totally symmetric with mixed pol...

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With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and e cient power estimation during the design phase is required in order to meet the power speci cations without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniqu...

ON DETECTION, ANALYSIS AND CHARACTERIZATION OF TRANSIENT AND PARAMETRIC FAILURES IN NANO-SCALE CMOS VLSI

This paper presents a low power MOS-VLSI implementation of an oscillator proposed by Freeman to model a very important component of the olfactory cortex [l]. The model dynamics has time constants in the order of 11220 (s). To accomplish the long time constants a new filtering technique recently proposed [2][3] was utilized. All the blocks involving information processing were designed to operat...