We present a 346 μm2 reference-free, asynchronous VCO-based sensor interface circuit demonstrated in 28 nm LP bulk CMOS. This design is specifically for sensor node interfaces which do not have the power or volume available for the high accuracy current sources, voltage sources, or low jitter timing references needed for traditional ADCs. By using a straightforward VCO design, it achieves wide ...

Aggressive power supply voltage Vdd scaling is widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical Vdd results to numerous setup timing errors, and hence to an unacceptable output quality. In this paper, we propose computation-skip (CS) scheme to mitigate setup timing errors, for recursive digital signa...

In the last decade, as the manufacturing companies have reconsidered the overall concept of goods production, their focus shifted from developing ‘products’ to ‘solutions’. In complex supply chains, the combination of products and services that maximize customers’ and stakeholders’ value can be identified only if manufacturers improve their ability to co-create, establishing more interactive re...

As integrated circuits technology sizes shrink, variability in process parameters, such as the threshold voltage, are expected to increase and become worse under low supply voltage (VDD). Circuit parameters, such as the propagation delay in logic gates and the resolution time from metastability in flipflops, will vary more. As a consequence, the synchronizer failure rate would be unpredictable....

This paper proposes a comprehensive SRAM cell optimization scheme that minimizes leakage power under ultra-low standby supply voltage (VDD). The theoretical limit of data retention voltage (DRV), the minimum VDD that preserves the states of a memory cell, was derived to be 50 mV for an industrial 90 nm technology. A DRV design model was developed on parameters including body bias, sizing, and c...

Epidemiologic data suggest that the incidence of food allergy (FA) is increasing among children, yet a satisfactory model of its pathogenesis remains elusive. FA is the consequence of maladaptive immune responses to common and otherwise innocuous food antigens. Concurrent with the increase in FA is an epidemic of vitamin D deficiency (VDD) caused by several factors, especially decreased sunligh...

This paper addresses the modeling of power supply voltage transients in digital systems, in order to estimate the system’s tolerance to this disturbance, in order to demonstrate EMI/EMC standard compliance. Electrical simulation is extensively used to demonstrate the possibility of exploiting the duality between time excitation and delay response, for combinational CUT (Circuit Under Test). We ...

AIMS The aim of this retrospective analysis was to investigate VDD mode survival, development of atrial tachyarrhythmias (AT), and long-term atrial sensing performance of VDD pacing systems. METHODS AND RESULTS We implanted single-lead VDD pacemakers in patients with isolated atrioventricular block and performed a retrospective analysis of 307 patients who had their devices implanted between ...

A CMOS/SOI circuit to decode PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a doubleintegration concept and does not require dc filtering. Nonoverlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good dis...

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. ...