OpenCL support across many heterogeneous nodes (FPGAs, GPUs, CPUs) has increased the programmability of these systems significantly. At the same time, it opens up new challenges and design choices for system designers and application programmers. While OpenCL offers a universal semantic to capture the parallel behavior of applications independent of the target architecture, some customization s...

It is well known that robotic manipulators are highly nonlinear coupling dynamic systems. It is difficult to establish an appropriate mathematical model for designing a model-based controller. The model-free feature of fuzzy logic control strategy was employed to design robotic motion controller. However, there is no guide rule for designing the fuzzy rule bank and parameters, it still needs ti...

Striped FPGA [1], or pipeline-recon gurable FPGA provides hardware virtualization by supporting fast run-time recon guration. In this paper we show that the performance of striped FPGA depends on the recon guration pattern, the run time scheduling of con gurations through the FPGA. We study two main con guration scheduling approachesCon guration Caching and Data Caching. We present the quantita...

This paper proposes the hardware architecture of face detection FPGA system using AdaBoost algorithm. The proposed structure is possible to work in 30 frames per second and real time. And algorithm adopted learn generate characteristics data by MATLAB, finally detected this data. describes composed image scaler, integral extraction, comparing, memory interface, grouper result display. circuit s...

Introduced in 1996 and greatly developed over the last few years, Lattice-based cryptography offers a whole set of primitives with nice features, including provable security and asymptotic efficiency. Going from “asymptotic” to “real-world” efficiency seems important as the set of available primitives increases in size and functionality. In this present paper, we explore the improvements that c...

An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilin...

Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconne...

A method for circular pattern recognition in a binary image and its implementation onto an FPGA are described. The proposed method is based on the template matching method using a modified matching degree. This method is implementable onto an FPGA and can realize a real-time system. The usefulness of the proposed method was confirmed by numerical simulations. The real-time performance was confi...