It is our opinion that the system-on-chip, all-in-one approach to parallel digital signal processing combining the homogeneous processor array with large amounts of data memory, will be the core of future embedded digital signal processing applications. In this paper we present two radical approaches to efficient system-on-chip (SoC) design with homogeneous processor arrays for real-time applic...

The increasing complexity of present SoCs demands new, scalable, reusable, parallel interconnection models for their cores. This paper presents a comparison study made in an on chip reconfigurable multiprocessor, the X4CP32, on its interconnection. Three models were proposed, a bus system, a SoC using FIFO buffering, and a SoC using SAFC buffering. All the models were described in SystemC and s...

This paper proposes a new methodology for testing a core-based system-on-a-chip (SOC), targeting the simultaneous reduction of test area overhead and test application time. At the core level, testability and transparency can be achieved by reusing existing logic inside the core, and providing different versions of the core having different area overheads and transparency latencies. At the chip ...

System-on-Chip (SoC) is a paradigm for designing today’s integrated circuit (IC) chips that puts an entire system onto a single silicon floor (instead of printed circuit boards containing a number of chips accomplishing the system task). With the increasing number of cores integrated on such a chip, on-chip communication efficiency has become one of the key factors in determining the overall sy...

– Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output r...

This paper presents a new programmable radio frequency (RF) system for a System-onChip (SoC) transceiver. A 5-GHz low noise amplifier (LNA) is integrated with an on-chip programmable RF circuits using 0.18μm SiGe technology. Proposed system is very useful for concurrent RF ICs in a complete RF system environment. The programmable circuit helps it to provide DC output voltages, hence, making the...

Network-on-Chip (NoC) replaces the traditional bus-based architecture to become the mainstream design methodology for future complex System-on-Chip (SoC). It introduces the principles of packet switching and interconnection network into SoC design, and achieves much better performance for its high bandwidth, scalability, reliability, etc. However, thermal problem, such as regional temperature d...

Test Methodologies for Globally Asynchronous Locally Synchronous (GALS) System On a Chip (SOC) are a subject of growing research interest since they appear to offer benefits in low power applications and promise greater design modularity. Pre-designed cores and reusable modules are popularly used in the design of large and complex Systems. As the size and complexity of System increase, the test...

In the broadest sense, a System-on-Chip (SOC) is a semiconductor product that incorporates significant circuit blocks (cores) from more than a single design group. Along this definition, every semiconductor manufacturer who has ever reused a large circuit design within a larger product has created a SOC, as has every ASIC designer who has ever used a foundry's memory arrays or largescale librar...