Traditional ADCs (Analog-to-Digital Converters) acquire samples at regular intervals TS at a sample rate fS=1/TS and needs to adhere to the Nyquist sampling theorem, i.e., fS>2 × fB, where fB is the signal’s bandwidth [1]. Due to the periodic nature of traditional ADCs, they are sometimes referred to as synchronous ADCs [2,3]. Synchronous ADCs are characterized by a periodicity in time and equi...

Synchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. The last decade has witnessed a resurgence of interest in asynchronous logic which promises to liberate digital design from the inherent problems of synchronous systems. This activity has revealed a need...

In this paper we propose a high-level description of the behavior of digital systems. Behaviors are specified with a graphical synchronous model: “SyncCharts”. SyncCharts supports hierarchical descriptions, concurrency and preemption. It is fully compatible with the programming environment of the Esterel synchronous language and can generate output formats understandable by synthesis tools. Tha...

Two digital systems working in different clock domains require a protocol to communicate with each other in order to ensure validity of the data being shared between the two systems. Such systems are said to be asynchronous, and the protocol used for communication is said to synchronize the two systems. Asynchronous design techniques are not as widely used as synchronous design techniques are. ...

This paper presents a new approach to logic synthesis of digital synchronous circuits. We present a model for synchronous circuits that supports logic transformations aimed at optimizing the circuit performance. Previous synthesis approaches attacked this problem by separating the combinational logic from the registers and by applying circuit transformations to the combinational component only....

This paper investigates specification, verification and test generation for synchronous and asynchronous circuits. The approach is called DILL (Digital Logic in LOTOS). DILL models are discussed for synchronous and asynchronous circuits. Relations for (strong) conformance are defined for verifying a design specification against a high-level specification. An algorithm is also outlined for gener...

A novel request-driven globally asynchronous locally synchronous (GALS) technique for the system integration of complex digital blocks is proposed. For this new GALS technique, an asynchronous wrapper compliant is developed and evaluated. This proposed GALS technique is applied to a baseband processor compatible with the wireless LAN standard IEEE 802.11a. The developed GALS baseband processor ...

This thesis presents a scheme that achieves self-stabilizing Byzantine digital clock synchronization assuming a “synchronous” system. This synchronous system is established by the assumption of a common external “beat” delivered with a regularity in the order of the network message delay, thus enabling the nodes to execute in lock-step. The system can be subjected to severe transient failures w...

We revisit a technique called round abstraction as a solution to the problem of building low-latency synchronous systems from asynchronous specifications. Although in general round abstraction is not compositional, we identify sufficient properties to guarantee correct composition, thereby proposing a framework for round abstraction that is totally correct when applied to asynchronous behaviour...

P ower consumption is becoming a critical concern in nowadays digital circuits’ design, especially for battery powered portable applications. In this context, asynchronous circuits represent one of the possible solutions for addressing power consumption issues, they can operate correctly at extremely low power supplies and are conceptually robust to PVT variation. This paper evaluates the power...