Ternary content addressable memories (TCAMs) perform high-speed lookup operation but when compared with static random access memories (SRAMs), TCAMs have certain limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and are very expensive. Thus, can we use the benefits of SRAM by configuring it (with additional logic) to enable it to behave li...

The results of 12 well-known and three fault-primitive-based memory test algorithms applied to 0.13 micron technology 512 kB single-port SRAMs are presented. Each test algorithm is used with up to 16 different stress combinations (SCs) (i.e. different address sequences, data backgrounds and voltages) resulting in 122 tests. The results show that SCs influence the fault coverage (FC) of the test...

SRAM based reprogrammable FPGA with high-flexibility combined with high-performance have become increasingly important for use in space applications. With the advances in technology, the device size decreasing below nm, FPGAs used in space environment are more susceptible to radiation. The radiation effects can cause Single Event Upset (SEU) which are soft-errors and non-destructive. This can a...

The Raw microprocessor consumes 122 million transistors, executes 16 different load, store, integer or floating point instructions every cycle, controls 25 GB/s of I/O bandwidth, and has 2 MB of on-chip, distributed L1 SRAM memory, providing on-chip memory bandwidth of 43 GB/s. Is this the latest billion-dollar 3,000 man-year processor effort? In fact, Raw was designed and implemented by a hand...

In this paper a detailed study of the effect of the phase of noise has been done on 6T SRAM cell. The 6T SRAM has been subjected to different combinations of noises at the storage nodes and the read ability and write ability of the SRAM cell is examined considering different noise voltage levels. It is found that the effect is different under different combinations of the phases of the noise vo...

Memory can be formed with the integration of large number of basic storing element called cells. SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit. Modified read and write circuits were proposed in this paper to address incorrect read and write operations in conventional 6T SRAM cell design available in open literature. Design of...

This paper describes an early memory yield prediction model using a memory sensitive area model. The proposed sensitive area prediction model calculates the sensitive area of a memory block for a given process technology and memory capacity. The model is capable of predicting the yield of a memory block in the early design phase without the detailed knowledge of the physical layout. The use of ...

The Present day workstations, low-power processors, computers and super computers are using fast Static Random Access Memory (SRAMs) and will require, in the future, larger density memories with faster access time and minimum power consumption. Acknowledging the intense requirements for power, in current high performance memories of computing devices, the circuit designers have developed a numb...

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as lowstorage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with addi...

A new Row-by-Row Dynamic Source-line Voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leak...