In low-voltage and low-power applications, optimization of several devices for speed and power is a significant issue. These issues can be overcome by incorporating Modified Gate Diffusion Input (Mod-GDI) technique. This technique has been adopted from Gate Diffusion Input (GDI). The Mod-GDI technique allows reducing power consumption, delay and area of digital circuits, while maintaining low c...

STATIC CMOS ICs WITH VERY LOW GLITCH POWER DISSIPATION NIHAR R. MAHAPATRA SRIRAM V. GARIMELLA ALWIN TAREEN [email protected] [email protected] [email protected] Department of Computer Science & Engineering VLSI Systems Group Department of Electrical Engineering State University of New York at Buffalo Seagate Technology, Inc. State University of New York at Buffalo Buffal...

Estimating and minimizing the maximum power dissipation during testing is an important task in VLSI circuit realization since the power value affects the reliability of the circuits. Therefore during testing a methodology should be adopted to minimize power consumption. Test patterns generated with –D 1 option of ATALANTA contains don’t care bits (x bits). By suitable filling of don’t cares can...

Dynamic Power by internal capacitance * Short-circuit Current Dissipation . ~ ~ ~ ~ ~ i ~ i ~ ~ i~~ 1 I Delay Abstract---It is known that input reordering of a gate affects the power dissipated by the internal capacitance of the reordered gate, which has been utilized for power reduction so far. We show that the reordering also has a significant effect on the power dissipation of the gate which...

Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits as the battery leaks even when devices are in idle state. To reduce leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this paper. Earlier w...

Load modeling is widely used in power system studies. Two types of modeling, namely, static and dynamic, are employed. The current industrial practice is the static modeling. Static modelss are algebraic equations of active and reactive power changes in terms of voltage and frequency deviations. In this paper, a component based on static modeling is employed in which the aggregate model is deri...

The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today‟s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits ...

With the advancement in semiconductor technology, chip density and operating frequency are increasing, so the power consumption in VLSI circuits has become a major problem of consideration. More power consumption increases packaging cost and also reduces the battery life of the devices. So it has become necessity of the VLSI circuits to reduce the dynamic as well as the static power consumption...

This paper studies the problems of minimizing power dissipation of an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing (BISWS). We consider two cases, namely minimizing power dissipation with optimal delay constraints, and minimizing power dissipation with a given delay penalty. We derive closed form optimal solutions for both cases. These closed form solu...

The first challenge, power dissipation, became evident at the beginning of this decade, and the importance has only grown in magnitude in the last several years. Power dissipation manifests as a problem in three fundamental ways: 1) high power dissipation is the primary performance limiter for mainstream highperformance microprocessors — it is simply not cost-effective to cool and deliver power...