b1-xlaxfeo3 (x = 0.0, 0.025) crystallites were prepared by chemical solution route. xrd analysis confirmed the phase formation of the materials. thermal characterization was done by dsc-tga to confirm crystallization and thermal behavior for phase development. morphological studies by fesem showed the agglomerated nature of the ferrite and edx analysis confirmed the degree of doping. ftir studi...

Mathematics is used in various fields of human life, one them the industrial field. In field mathematics can be finding shortest route distributing gas. Finding was done using Dijkstra's algorithm and developing Python programming language. The purpose this study to determine on gas distribution at PT Tira Austenite Tbk Cikarang This type research applied research. results obtained from are lan...

The watchman route problem (WRP) was first introduced in 1988 and is defined as follows: How to calculate a shortest route completely contained inside a simple polygon such that any point inside this polygon is visible from at least one point on the route? So far the best known result for the WRP is an O(nlogn) runtime algorithm (with inherent numerical problems of its implementation). This pap...

Covert channels are of two types: (a) timing channel and (b) storage channel. Most previous works have studied these channels from the encoder’s perspective, namely, information theoretic capacity, algorithms and protocols for hiding information etc. This paper investigates the covert channel problem from an passive adversary’s perspective. A sequential distinguisher for storage channel identif...

Conformant probabilistic planning (CPP) differs from conformant planning (CP) by two key elements: the initial belief state is probabilistic, and the conformant plan must achieve the goal with probability ≥ θ, for some 0 < θ ≤ 1. In earlier work we observed that one can reduce CPP to CP by finding a set of initial states whose probability≥ θ, for which a conformant plan exists. In previous solv...

Timing analysis spans the entire design process from RTL synthesis to timing sign-off including schematic design, logic synthesis, floor plan, place and route, clock distribution etc. In this embedded tutorial we will cover timing analysis from devices to systems. At the transistor level we will cover static, dynamic and interconnect analysis. At the gate level we will cover path analysis inclu...