In this work the problem of modeling reconfigurable systems behavior with a precise, executable semantics is considered. The possibility of synthesising such models onto reconfigurable technologies is also faced. The modeling problem is tackled with the definition of a formalism based on the possibility of Java to vary its class pool at run-time. Feasibility of the sinthesis approach is verifie...

Self-Reconfigurable robots are complex distributed systems composed of multiple modular robotic units. These units can rearrange to form different structures that fit the specific tasks that face the robot. The unique and complex nature of self-reconfigurable robots has lead to a challenging subset of motion-planning problems. In this paper several types of reconfigurable robots are described a...

This paper introduces an approach to model checking of reconfigurable Petri nets. The main task is to flatten the two levels of dynamic behavior that reconfigurable nets provide, the firing of transitions on the one hand and the transformation of the nets on the other hand. We show how to translate a reconfigurable net into Maude modules. Maude’s LTL model-checker is then used to verify propert...

We present a runtime environment that partially reconfigures and executes hardware tasks on Xilinx Virtex. To that end, the FPGA’s reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the hardware tasks. A bus-based communication infrastructure allows for task communication and I/O. We discuss the design of the runtime system and its p...

Reconfigurable Computers are general-purpose high-end computers based on a hybrid architecture and close system-level integration of traditional microprocessors and Field Programmable Gate Arrays (FPGAs). It is expected that programming of reconfigurable computers should not require any knowledge of hardware design, assuming that sufficiently large library of elementary operations has been earl...

An imperative requirement in the design of a reconfigurable computing system or in the development of a new application on such a system is performance gains. However, such developments suffer from long-and-difficult programming process, hard-to-predict performance gains, and limited scope of applications. To address these problems, we need to understand reconfigurable hardware’s capabilities a...

A new reconfigurable active router architecture is presented in this paper. It consists of a software part and a hardware part. The software part is a set of kernelspace and user-space modules running on linux-PC. An FPGA PCI-based board with a Virtex-1600E FPGA forms the hardware part. The integration of reconfigurable hardware into standard PC hardware allows for on-the-fly reconfigurable har...

Reconfigurable processing units promise to boost the performance of computational intensive applications. Thereby the kernel of an application is executed in the reconfigurable hardware instead of being executed in software. This report presents a reconfigurable extension for the CarCore embedded processor. The extension combines reconfigurability with simultaneous multithreading and real-time ...

This paper presents PNETMAP, an algorithm that maps virtual communication networks of a Cyber Physical System onto a partially-known, physical network of reconfigurable embedded systems. The paper describes in detail the algorithm and offers an extensive set of experimental results on the quality of the produced communication structures for different network topologies. Experiments use a networ...