processor, making the scheduler partition-aware can lead to inter-core locality benefits for other structures as well. For example, in Delaunay mesh generation, this data-centric scheduling policy ensures that different cores work on triangles from different partitions of the mesh, reducing data contention and the likelihood of speculation conflicts. It is not clear that data-centric scheduling...

Most modern processors offer hardware support for monitoring performance events related to the interaction of applications with specific subunits of the processor [4, 7, 8, 9, 10]. The insight attained from performance monitoring counters is useful for both application programmers and processor manufacturers. Programmers typically employ them as a powerful tool for post-mortem analysis, identif...

ENERGY CONSUMPTION is today an important design issue for all kinds of digital systems, and essential for the battery operated ones. An important fraction of this energy is dissipated on the processors running the application software. To reduce this energy consumption, one may, for instance, lower the processor clock frequency and supply voltage. This, however, might lead to a performance degr...

This report discusses the similarities and the differences betweenmachine scheduling problems, and instruction scheduling problems on modern VLIW processors such as the STMicroelectronics ST200. Our motivations are to apply the machine scheduling techniques that are relevant to instruction scheduling in VLIW compilers, and to understand how processor micro-architecture features impact advanced ...

In the area of Computer Science, Parallel job scheduling is an important field of research. Finding a best suitable processor on the high performance or cluster computing for user submitted jobs plays an important role in measuring system performance. A new scheduling technique called communication aware scheduling is devised and is capable of handling serial jobs, parallel jobs, mixed jobs and...

Scheduling precedence graphs with communication times is the theoretical basis for achieving efficient parallelism in message-passing machines. The lack of global information on the tasks, due to communication, has lead to develop local scheduling heuristics such as the Earliest-Task-First. Using knowledge on computation, communication, and system topology, a class of global priority-based sche...

In this paper, we focus on the semi-partitioned scheduling of sporadic tasks with constrained deadlines and identical processors. We study two cases of semi-partitioning: (i) the case where the Worst Case Execution Time (WCET) of a job can be portioned, each portion being executed on a dedicated processor, according to a static pattern of migration; (ii) the case where the jobs of a task are re...

Energy consumption is a critical design issue in real-time systems, especially in batteryoperated systems. Maintaining high performance, while extending the battery life between charges is an interesting challenge for system designers. Dynamic Voltage Scaling (DVS) allows a processor to dynamically change speed and voltage at run time, thereby saving energy by spreading run cycles into idle tim...

This paper deals with two-processor scheduling for a class of program nets, that are acyclic and SWITCH-less, and of which each node has unity node firing time. Firstly, we introduce a hybrid priority list L∗ that generates optimal schedules for the nets whose AND-nodes possess at most single input edge. Then we extend L∗ to suit for general program nets to give a new priority list L∗∗. Finally...

17 SCHEDULING AND LOAD BALANCING This paper presented a static scheduling heuristic called best-imaginary-level(BIL) scheduling for heterogeneous processors. The input graph is an acyclic precedence graph, where a node has diierent execution times on diierent processors. The static level of a node, or BIL, incorporates the eeect of interprocessor communication (IPC) overhead and processor heter...