In this paper, new hardware architecture of multiplier and accumulator (MAC) for high speed arithmetic was designed. The performance was improved by merging multiplication with accumulation and organize a hybrid type carry save adder (CSA). The proposed CSA tree uses 1's complement based radix-4 and radix-8 modified booth algorithm(MBA). The CSA propagates the carries to the least signific...

In the majority of digital signal processing (DSP) applications the critical operations are the multiplication and accumulation. Real-time signal processing requires high speed and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which is always a key to achieve a high performance digital signal processing system. The purpose of this work is, design and implementation ...

Finite Difference (FD) methods are the most prevalent numerical modelling algorithms for evaluating initial or boundary value problems in scientific and engineering applications. Unfortunately, simulating time evolutions for transient physical phenomenon is computationally demanding and data-intensive. In this paper, we introduce an efficient implementation of FD computing engine on FPGA-based ...

Transmission and distribution pipelines have a significant role in the oil and gas industries. Pipelines are facing different threat like corrosion, improper design and incorrect operation. Gas vapor released from a pipeline (owned by NIOC) failure spread out and reached to ignition source. Due to gas outdoor spreading, “flash fire” occurred and flame return caused “vapor cloud explosion” of ga...

Signal processing is a data processing domain that contains a diversity of applications, including speech processing, image processing, radar, sonar, medical imaging, data communications, seismic processing, and many others. Despite the diversity of the applications, this processing domain has a very structured set of characteristics. These include real-time operation. dominance of arithmetic o...

This paper presents a 12 GHz direct digital synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 m SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current-steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of the DDS MMIC is measured as 11.9 GHz at t...

In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. This can be implement by using radix-2 booth encoder .By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. This includes the design exploration and applications of a spurious-power suppression technique (SPST) w...

In this paper, we demonstrate that the construction proposed by Lan Nguyen at CT-RSA’05 does lead to a cryptographic accumulator which is not collision resistant.